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91. 发明授权

US08933515B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08933515B2
公开(公告)日：2015-01-13
申请号：US13531175
申请日：2012-06-22
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

92. 发明授权

US08927387B2 Robust isolation for thin-box ETSOI MOSFETS 有权
标题翻译：薄型ETSOI MOSFET的强大隔离性
公开(公告)号：US08927387B2
公开(公告)日：2015-01-06
申请号：US13442168
申请日：2012-04-09
申请人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
IPC分类号： H01L27/088 , H01L21/336 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76283 , H01L27/1203
摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要翻译：薄型BOX ETSOI器件，具有强大的隔离性和制造方法。该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层，第一半导体晶片上的栅极结构。

93. 发明授权

US08803233B2 Junctionless transistor 有权
标题翻译：无结晶体晶体管
公开(公告)号：US08803233B2
公开(公告)日：2014-08-12
申请号：US13242861
申请日：2011-09-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
摘要翻译：晶体管包括半导体层，并且在半导体层上形成栅极电介质。栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。该渐变掺杂剂区域的掺杂浓度逐渐降低。晶体管还包括与有源区相邻的源区和漏区。源极和漏极区域和有源区域具有相同的导电类型。

94. 发明授权

US08741701B2 Fin structure formation including partial spacer removal 有权
标题翻译：翅片结构形成包括部分间隔物去除
公开(公告)号：US08741701B2
公开(公告)日：2014-06-03
申请号：US13585395
申请日：2012-08-14
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L29/66795
摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.
摘要翻译：形成半导体器件的方法包括：在基底的顶部上形成心轴; 在所述基板的顶部上形成邻近所述心轴的第一间隔件; 在第一间隔件和心轴上形成切割掩模，使得第一间隔件被切割掩模部分地暴露; 部分地去除部分暴露的第一间隔件; 并且蚀刻所述衬底以形成对应于所述衬底中部分移除的第一间隔物的翅片结构。

95. 发明申请

US20140048804A1 FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL 审中-公开
公开(公告)号：US20140048804A1
公开(公告)日：2014-02-20
申请号：US13589427
申请日：2012-08-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
IPC分类号： H01L29/04
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L29/66795
摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

96. 发明授权

US08642415B2 Semiconductor substrate with transistors having different threshold voltages 失效
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US08642415B2
公开(公告)日：2014-02-04
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：公开了一种制造半导体集成电路的方法。该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

97. 发明授权

US08617937B2 Forming narrow fins for finFET devices using asymmetrically spaced mandrels 有权
标题翻译：使用不对称间隔的心轴形成finFET器件的窄鳍
公开(公告)号：US08617937B2
公开(公告)日：2013-12-31
申请号：US12886850
申请日：2010-09-21
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L29/66795 , H01L21/845
摘要： A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的鳍片的方法包括在半导体衬底上形成多个牺牲心轴。多个牺牲心轴沿着第一方向彼此间隔开第一距离，并且沿第二方向间隔开第二距离。间隔层形成在牺牲心轴的侧壁上，使得沿着第一方向的牺牲心轴之间的间隔层的部分被合并在一起。沿着第二方向的牺牲心轴之间的间隔层的部分保持间隔开。牺牲心轴被去除。对应于间隔层的图案被转移到半导体层中以形成多个半导体鳍片。相邻的翅片对在与合并的间隔层相对应的位置处彼此合并。

98. 发明授权

US08598664B2 Field effect transistor (FET) and method of forming the FET without damaging the wafer surface 有权
标题翻译：场效应晶体管（FET）和形成FET而不损坏晶片表面的方法
公开(公告)号：US08598664B2
公开(公告)日：2013-12-03
申请号：US13420763
申请日：2012-03-15
申请人： Kangguo Cheng , Bruce B. Doris , Yu Zhu
发明人： Kangguo Cheng , Bruce B. Doris , Yu Zhu
IPC分类号： H01L27/12
CPC分类号： H01L21/28 , H01L29/78
摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.
摘要翻译：公开了场效应晶体管结构和形成该结构的方法。栅极叠层形成在指定沟道区上方的晶片上。间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

99. 发明授权

US08564040B1 Inversion mode varactor 有权
标题翻译：反转模式变容二极管
公开(公告)号：US08564040B1
公开(公告)日：2013-10-22
申请号：US13570360
申请日：2012-08-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层，其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

100. 发明申请

US20130207189A1 INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME 有权
标题翻译：具有降低硅氧烷接触电阻的上升源排水装置的集成电路及其制造方法
公开(公告)号：US20130207189A1
公开(公告)日：2013-08-15
申请号：US13852103
申请日：2013-03-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

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