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91. 发明授权

US07733720B2 Method and system for determining element voltage selection control values for a storage device 失效
标题翻译：用于确定存储设备的元件电压选择控制值的方法和系统
公开(公告)号：US07733720B2
公开(公告)日：2010-06-08
申请号：US11941161
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/41 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/72
摘要： A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.
摘要翻译：用于确定存储设备的元件电压选择控制值的方法和系统在保持特定性能水平的同时在存储阵列中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。在测试时间，除非要求该元件满足性能要求，否则需要为虚拟电源轨设置最小电源电压的每个元件的选择电路确定数字控制值。然后可以将该组数字控制值编程为保险丝或用于在制造时调整掩模，或者与存储设备一起提供在介质上并在系统初始化时加载到设备中。

92. 发明申请

US20090172451A1 METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有全元选择电源电压的存储设备的方法和计算机程序
公开(公告)号：US20090172451A1
公开(公告)日：2009-07-02
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非该元件需要较高的电源电压以满足性能要求。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

93. 发明申请

US20080209285A1 Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks 失效
标题翻译：用于测量测试电路块阵列内各个块的工作和泄漏电流的方法和电路
公开(公告)号：US20080209285A1
公开(公告)日：2008-08-28
申请号：US11679346
申请日：2007-02-27
申请人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
发明人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
IPC分类号： G01R31/28
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/3008 , G01R31/318575
摘要： A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.
摘要翻译：用于测量测试电路块阵列内的各个块的工作和漏电流的方法和电路提供了通过未选择的电路块的漏电流而无误差的测量，而不需要每个电路块的独立测试设施。电路包括一对电源网格和每个测试电路块上的选择电路，用于在测试电网和用于向未选择电路提供电流的“静止”电网之间进行选择。因此，通过非选择电路的泄漏电流源于剩余电网，避免了在测试电网电流测量中引入的误差。测试电路块可以是环形振荡器，并且所测量的电流可以是环形振荡器的工作和/或泄漏电流。电路块还可以包括用于使用附加栅极输入栅格的IV（电流 - 电压）表征的单独器件。

94. 发明授权

US08473879B2 On-chip leakage current modeling and measurement circuit 失效
标题翻译：片内漏电流建模与测量电路
公开(公告)号：US08473879B2
公开(公告)日：2013-06-25
申请号：US13484868
申请日：2012-05-31
申请人： Rajiv V. Joshi , Rousaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rousaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

95. 发明申请

US20130014069A1 Equivalent Device Statistical Modeling for Bitline Leakage Modeling 有权
标题翻译：用于位线泄漏建模的等效装置统计建模
公开(公告)号：US20130014069A1
公开(公告)日：2013-01-10
申请号：US13616991
申请日：2012-09-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.
摘要翻译：提供了用于将集成电路设计的多个装置建模为单个统计上等同的宽装置的机构。分析集成电路设计以识别具有多个装置的集成电路设计的一部分。对于多个装置，产生统计模型的单个统计学上等效的宽装置，该统计模型具有捕获多个装置中的各个装置的统计工作特性分布的单个统计学等效的宽装置的至少一个操作特性的统计分布。单个统计学等效的宽设备的至少一个统计工作特性是各个设备的统计操作特性的复杂非线性函数。集成电路设计采用单一统计学上等效的宽设备进行建模。

96. 发明授权

US08245159B2 Gradient based search mechanism for optimizing photolithograph masks 有权
标题翻译：基于梯度的搜索机制，用于优化光刻胶掩模
公开(公告)号：US08245159B2
公开(公告)日：2012-08-14
申请号：US12536090
申请日：2009-08-05
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.
摘要翻译：提供了一种用于优化光刻胶掩模的机构。收到给定的目标模式。从给定的目标图案生成初始虚拟掩模，并且选择初始值α2，其中使用初始值α2来确定光强度和晶片图像。然后确定初始虚拟掩模中的每个像素的光强度和初始虚构掩模中每个像素的晶片图像。然后通过将从虚构掩模生成的晶片图像与给定的目标图案进行比较来确定是否实现了会聚。响应于从虚构掩模生成的晶片图像到给定目标图案的会聚，产生用于将图像转印到晶片的最终掩模。

97. 发明申请

US20110225438A1 COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有各元件选择电源电压的存储设备的计算机程序产品
公开(公告)号：US20110225438A1
公开(公告)日：2011-09-15
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

98. 发明申请

US20100313070A1 BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS 有权
标题翻译：改进的多故障区域故障概率分析方法
公开(公告)号：US20100313070A1
公开(公告)日：2010-12-09
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F11/26
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

99. 发明申请

US20090319202A1 Delay-Based Bias Temperature Instability Recovery Measurements for Characterizing Stress Degradation and Recovery 失效
标题翻译：基于延迟的偏压温度不稳定性恢复测量，用于表征应力退化和恢复
公开(公告)号：US20090319202A1
公开(公告)日：2009-12-24
申请号：US12142294
申请日：2008-06-19
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L1/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

100. 发明授权

US07550987B2 Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks 失效
标题翻译：用于测量测试电路块阵列内各个块的工作和漏电流的方法和电路
公开(公告)号：US07550987B2
公开(公告)日：2009-06-23
申请号：US11679346
申请日：2007-02-27
申请人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
发明人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/3008 , G01R31/318575
摘要： A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.
摘要翻译：用于测量测试电路块阵列内的各个块的工作和漏电流的方法和电路提供了通过未选择的电路块的漏电流而无误差的测量，而不需要每个电路块的独立测试设施。电路包括一对电源网格和每个测试电路块上的选择电路，用于在测试电网和用于向未选择电路提供电流的“静止”电网之间进行选择。因此，通过非选择电路的泄漏电流源于剩余电网，避免了在测试电网电流测量中引入的误差。测试电路块可以是环形振荡器，并且所测量的电流可以是环形振荡器的工作和/或泄漏电流。电路块还可以包括用于使用附加栅极输入栅格的IV（电流 - 电压）表征的单独器件。

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