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91. 发明授权

US08476150B2 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08476150B2
公开(公告)日：2013-07-02
申请号：US12887797
申请日：2010-09-22
申请人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
发明人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02107
摘要： A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.
摘要翻译：一种用于半导体器件的方法和结构，所述器件包括处理晶片，直接形成在所述手柄晶片前侧上的金刚石层以及直接形成在所述手柄晶片的背面上的厚氧化物层，所述氧化物抵抗金刚石层的拉伸应力的厚度。在金刚石层和厚氧化物层的外表面上形成氮化物层，并且在氮化物层的外表面上形成多晶硅。器件晶片被结合到处理晶片以形成半导体器件。

92. 发明申请

US20120313201A1 OPTICAL SENSOR DEVICES INCLUDING FRONT-END-OF-LINE (FEOL) OPTICAL FILTERS AND METHODS FOR FABRICATING OPTICAL SENSOR DEVICES 审中-公开
标题翻译：包括前端（FEOL）光学滤波器的光学传感器装置和用于制造光学传感器装置的方法
公开(公告)号：US20120313201A1
公开(公告)日：2012-12-13
申请号：US13466867
申请日：2012-05-08
申请人： Francois Hebert , Jonathan Herman , I-Shan Sun
发明人： Francois Hebert , Jonathan Herman , I-Shan Sun
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： G02B5/285 , H01L31/02165 , H01L31/103
摘要： Optical sensor devices, and methods of manufacturing the same, are described herein. In an embodiment, a monolithic optical sensor device includes a semiconductor substrate having a trench, with a photodetector region under said trench. An optical filter is formed in the trench and over at least a portion of the photodetector region. One or more metal structures extend above a top surface of said optical filter. The trench, photodetector region and optical filter are formed as part of a front-end-of-line (FEOL) semiconductor fabrication process. The one or more metal structures are formed as part of a back-end-of-line (BEOL) semiconductor fabrication process.
摘要翻译：光传感器装置及其制造方法在此描述。在一个实施例中，单片光学传感器装置包括具有沟槽的半导体衬底，在所述沟槽下方具有光电检测器区域。滤光器形成在沟槽中并且在光电检测器区域的至少一部分上方。一个或多个金属结构在所述滤光器的顶表面上方延伸。沟槽，光电检测器区域和滤光器形成为前端（FEOL）半导体制造工艺的一部分。一个或多个金属结构形成为后端（BEOL）半导体制造工艺的一部分。

93. 发明申请

US20120288083A1 SYSTEMS AND METHODS FOR FORMING ISOLATED DEVICES IN A HANDLE WAFER 有权
标题翻译：用于在手轮中形成分离的装置的系统和方法
公开(公告)号：US20120288083A1
公开(公告)日：2012-11-15
申请号：US13283139
申请日：2011-10-27
申请人： I-Shan Sun , Rick Carlton Jerome , Francois Hebert
发明人： I-Shan Sun , Rick Carlton Jerome , Francois Hebert
IPC分类号： H02H9/04 , H01L23/48 , H04M1/60 , H01L21/50
CPC分类号： H01L29/66204 , H01L21/743 , H01L23/481 , H01L23/535 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.
摘要翻译：提供了一种通过积分硅通过集成的方法。该方法包括在处理晶片中形成电气装置。该方法还包括在手柄晶片和电气装置上形成隔离层，并将活性层连接到隔离层。此外，该方法包括通过有源层和隔离层形成至少一个沟槽，以暴露处理晶片的一部分并在至少一个沟槽中沉积导电材料，导电材料提供与电设备通过活动层。

94. 发明申请

US20110163434A1 STACKED POWER CONVERTER STRUCTURE AND METHOD 有权
标题翻译：堆叠式电力转换器结构与方法
公开(公告)号：US20110163434A1
公开(公告)日：2011-07-07
申请号：US13048165
申请日：2011-03-15
申请人： David B. Bell , Francois Hebert , Nikhil Kelkar
发明人： David B. Bell , Francois Hebert , Nikhil Kelkar
IPC分类号： H01L23/495 , H01L23/52
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
摘要翻译：功率转换器可以包括具有可形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。功率转换器还可以包括形成在不同管芯上的控制器集成电路（IC），其可以与PowerDie电耦合并与其一体化。 PowerDie可以附接到引线框架的管芯焊盘，并且控制器IC管芯可以附接到第一管芯的有源表面，使得第一管芯插在控制器IC管芯和管芯焊盘之间。

95. 发明申请

US20110073943A1 TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS 有权
标题翻译：基于底层源LDMOS的真正CSP功率MOSFET
公开(公告)号：US20110073943A1
公开(公告)日：2011-03-31
申请号：US12965778
申请日：2010-12-10
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7835 , H01L24/05 , H01L24/45 , H01L29/0692 , H01L29/402 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/781 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05556 , H01L2224/45124 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2224/48 , H01L2924/00
摘要： A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.
摘要翻译：半导体封装可以包括半导体衬底，具有形成在衬底上的多个单元的MOSFET器件，以及设置在衬底的底部上的所有单元共用的源极区域。每个单元包括在半导体器件的顶部上的漏极区域，用于控制源极和漏极区域之间的电流的栅极，靠近栅极的源极接触点; 以及源极接触和源极区域之间的电连接。至少一个漏极连接电连接到漏极区域。源极，漏极和栅极焊盘电连接到器件的源极区域，漏极区域和栅极。漏极，源极和栅极焊盘形成在半导体封装的一个表面上。电池分布在衬底上，由此每个器件的源极接触和源极区之间的电连接分布在衬底上。

96. 发明申请

US20100163979A1 TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS 有权
标题翻译：基于底层源LDMOS的真正CSP功率MOSFET
公开(公告)号：US20100163979A1
公开(公告)日：2010-07-01
申请号：US12345467
申请日：2008-12-29
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L24/05 , H01L24/45 , H01L29/0692 , H01L29/402 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/781 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05556 , H01L2224/45124 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2224/48 , H01L2924/00
摘要： A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.
摘要翻译：半导体封装可以包括半导体衬底，具有形成在衬底上的多个单元的MOSFET器件和设置在衬底的底部上的所有单元共用的源极区域。每个单元包括在半导体器件的顶部上的漏极区域，用于控制源极和漏极区域之间的电流流动的栅极，靠近栅极的源极接触; 以及源极接触和源极区域之间的电连接。至少一个漏极连接电连接到漏极区域。源极，漏极和栅极焊盘电连接到器件的源极区域，漏极区域和栅极。漏极，源极和栅极焊盘形成在半导体封装的一个表面上。电池分布在衬底上，由此每个器件的源极接触和源极区之间的电连接分布在衬底上。

97. 发明申请

US20090166722A1 High voltage structures and methods for vertical power devices with improved manufacturability 审中-公开
标题翻译：具有改进可制造性的垂直功率器件的高电压结构和方法
公开(公告)号：US20090166722A1
公开(公告)日：2009-07-02
申请号：US12005878
申请日：2007-12-28
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727
摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.
摘要翻译：本发明公开了一种半导体功率器件，其设置在支撑外延层的半导体衬底上，作为由外延层构成的漂移区。半导体功率器件还包括超结结构，其包括设置在多个外延层中的多个掺杂侧壁。外延层具有多个沟槽，其中多个外延层开放并填充，其中掺杂的列沿着设置在多个外延层中的沟槽的侧壁设置。

98. 发明申请

US20080242052A1 Method of forming ultra thin chips of power devices 审中-公开
标题翻译：形成功率器件超薄芯片的方法
公开(公告)号：US20080242052A1
公开(公告)日：2008-10-02
申请号：US11694888
申请日：2007-03-30
申请人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/30
CPC分类号： H01L21/3043 , H01L21/78
摘要： A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes: Thinning wafer central portion from its back-side to produce a thin region while preserving original wafer thickness in the wafer periphery for structural strength. Forming ohmic contact at wafer back-side. Separating and collecting pre-fabricated devices. This further includes: Releasably bonding wafer back-side onto single-sided dicing tape, in turn supported by a dicing frame. Providing a backing plate to match the thinned out wafer central portion. Sandwiching the dicing tape between wafer and backing plate then pressing the dicing tape to bond with the wafer. With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.
摘要翻译：公开了制造薄半导体器件的方法。从具有预制的前端器件的晶片开始，该方法包括：从其背面将晶片中心部分变薄以产生薄区域，同时在晶片周边保留原始晶片厚度以获得结构强度。在晶圆背面形成欧姆接触。分离和收集预制设备。这还包括：将晶片背面可释放地粘合到单面切割胶带上，然后由切割架支撑。提供背板以匹配变薄的晶片中心部分。将切割胶带夹在晶片和背板之间，然后按压切割胶带与晶片结合。利用阶梯型卡盘来支撑晶片背面，在一个切割操作中，预制的装置彼此分离并且与晶片周边分离，切割深度比晶片中心部分稍厚。然后拾取并收集分离的薄半导体器件。

99. 发明申请

US20080180871A1 Structure and method for self protection of power device 有权
标题翻译：电力设备自保护结构及方法
公开(公告)号：US20080180871A1
公开(公告)日：2008-07-31
申请号：US11657862
申请日：2007-01-25
申请人： Francois Hebert , Ming Sun
发明人： Francois Hebert , Ming Sun
IPC分类号： H02H5/04 , H01L21/60
CPC分类号： H01L25/18 , H01L23/62 , H01L24/48 , H01L24/49 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49111 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/19043 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.
摘要翻译：可复位的过流自保护半导体功率器件包括垂直功率半导体芯片和由诸如PTC材料的限流材料构成的过电流保护层。过电流保护层可以夹在垂直功率半导体芯片和导电板之间，该导电板可以是装置安装在其上的引线框，金属板，PCB板或PCB。

100. 发明申请

US20080150013A1 Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer 审中-公开
标题翻译：用高密度等离子体（HDP）氧化层形成分离栅，作为多晶硅间绝缘层
公开(公告)号：US20080150013A1
公开(公告)日：2008-06-26
申请号：US11644344
申请日：2006-12-22
申请人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译：本发明公开了一种制造半导体功率器件的方法，该沟槽半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部和底部栅极段之间的多晶硅绝缘层分开。该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

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