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1. 发明申请

US20080150013A1 Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer 审中-公开
标题翻译：用高密度等离子体（HDP）氧化层形成分离栅，作为多晶硅间绝缘层
公开(公告)号：US20080150013A1
公开(公告)日：2008-06-26
申请号：US11644344
申请日：2006-12-22
申请人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译：本发明公开了一种制造半导体功率器件的方法，该沟槽半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部和底部栅极段之间的多晶硅绝缘层分开。该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

2. 发明授权

US08053315B2 Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer 有权
标题翻译：用高密度等离子体氧化物层制造分裂栅的多晶硅绝缘层的方法
公开(公告)号：US08053315B2
公开(公告)日：2011-11-08
申请号：US12589045
申请日：2009-10-16
申请人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译：本发明公开了一种制造沟槽半导体功率器件的方法，该半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部栅极段和底部栅极段之间的多晶硅绝缘层分开。该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

3. 发明申请

US20100099230A1 Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer 有权
标题翻译：用高密度等离子体氧化物层制造分裂栅的多晶硅绝缘层的方法
公开(公告)号：US20100099230A1
公开(公告)日：2010-04-22
申请号：US12589045
申请日：2009-10-16
申请人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译：本发明公开了一种制造沟槽半导体功率器件的方法，该半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部栅极段和底部栅极段之间的多晶硅绝缘层分开。该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

4. 发明授权

US08471368B2 Polysilicon control etch back indicator 失效
标题翻译：多晶硅控制回蚀指示器
公开(公告)号：US08471368B2
公开(公告)日：2013-06-25
申请号：US13431551
申请日：2012-03-27
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/06
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

5. 发明申请

US20090148995A1 Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) 有权
标题翻译：用于制造具有过多圆形屏蔽栅极沟槽（SGT）的MOSFET器件的工艺
公开(公告)号：US20090148995A1
公开(公告)日：2009-06-11
申请号：US12378040
申请日：2009-02-09
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole.
摘要翻译：本发明公开了一种用于制造沟槽金属氧化物半导体场效应晶体管（MOSFET）器件的改进方法。该方法包括在衬底中打开沟槽并且用亚麻层覆盖沟槽的沟槽壁，然后从沟槽的底部去除一部分亚麻层的步骤。该方法还包括通过在沟槽的底部施加各向同性的基底蚀刻来打开圆孔的步骤，其中圆形孔从沟槽壁横向延伸。该方法还包括用栅极材料填充沟槽底部的沟槽和圆孔，然后施加时间蚀刻以从沟槽的顶部去除栅极材料的步骤，由此栅极材料仅填充圆形孔直到圆孔的侧向膨胀点。

6. 发明申请

US20110198588A1 Polysilicon control etch-back indicator 有权
标题翻译：多晶硅控制回蚀指示器
公开(公告)号：US20110198588A1
公开(公告)日：2011-08-18
申请号：US13066583
申请日：2011-04-18
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

7. 发明申请

US20100084707A1 Polysilicon control etch-back indicator 有权
标题翻译：多晶硅控制回蚀指示器
公开(公告)号：US20100084707A1
公开(公告)日：2010-04-08
申请号：US12653130
申请日：2009-12-09
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/78 , H01L23/544 , H01L21/336
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

8. 发明授权

US07932148B2 Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) 有权
标题翻译：用于制造具有过多圆形屏蔽栅极沟槽（SGT）的MOSFET器件的工艺
公开(公告)号：US07932148B2
公开(公告)日：2011-04-26
申请号：US12378040
申请日：2009-02-09
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.
摘要翻译：本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

9. 发明授权

US07492005B2 Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes 有权
标题翻译：过多的圆孔屏蔽栅沟槽（SGT）MOSFET器件和制造工艺
公开(公告)号：US07492005B2
公开(公告)日：2009-02-17
申请号：US11321957
申请日：2005-12-28
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.
摘要翻译：本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅极。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

10. 发明申请

US20120193631A1 POLYSILICON CONTROL ETCH BACK INDICATOR 失效
标题翻译：多晶硅控制回退指示器
公开(公告)号：US20120193631A1
公开(公告)日：2012-08-02
申请号：US13431551
申请日：2012-03-27
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

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