专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07683418B2 High-temperature stable gate structure with metallic electrode 失效
标题翻译：具有金属电极的高温稳定栅极结构
公开(公告)号：US07683418B2
公开(公告)日：2010-03-23
申请号：US12277539
申请日：2008-11-25
申请人： Dae-Gyu Park , Oleg G. Gluschenkov , Michael A. Gribelyuk , Kwong Hon Wong
发明人： Dae-Gyu Park , Oleg G. Gluschenkov , Michael A. Gribelyuk , Kwong Hon Wong
IPC分类号： H01L27/108
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.
摘要翻译：本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

92. 发明申请

US20100055442A1 METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES 审中-公开
标题翻译： SiNxCy的PE-AlD方法和多孔低K基体上衬层材料的整合
公开(公告)号：US20100055442A1
公开(公告)日：2010-03-04
申请号：US12203338
申请日：2008-09-03
申请人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
发明人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
IPC分类号： C23C16/513 , B32B3/26
CPC分类号： C23C16/45536 , C23C16/36 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02203 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/3141 , H01L21/3148 , H01L21/31695 , H01L21/3185 , H01L21/76826 , H01L21/76831 , Y10T428/24999
摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.
摘要翻译：一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是防止在基板的表面的孔内渗透。还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

93. 发明申请

US20090283838A1 Fabrication of self-aligned CMOS structure 有权
标题翻译：自对准CMOS结构的制作
公开(公告)号：US20090283838A1
公开(公告)日：2009-11-19
申请号：US12120658
申请日：2008-05-15
申请人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
摘要翻译：公开了一种用于制造CMOS结构的方法。该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。之后是在NFET器件和PFET器件上的Al层的覆盖布置。该方法还包括在Al层上共享的栅极金属层的布置布置。当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

94. 发明授权

US07611979B2 Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks 有权
标题翻译：具有低电荷捕获的金属栅极和用于高k栅极电介质叠层的增强的电介质可靠性特性
公开(公告)号：US07611979B2
公开(公告)日：2009-11-03
申请号：US11673901
申请日：2007-02-12
申请人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
发明人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
摘要翻译：提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

95. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

96. 发明申请

US20090108372A1 SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS 有权
标题翻译：具有平面通孔和平面拉低NFET的矩形组合有源区的SRAM单元
公开(公告)号：US20090108372A1
公开(公告)日：2009-04-30
申请号：US11924059
申请日：2007-10-25
申请人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
发明人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , H01L27/11
摘要： A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
摘要翻译：平面通栅NFET被设计成具有与平面下拉NFET相同的宽度。为了优化平面下拉NFET和邻接的平面通过栅极NFET之间的β比率，通过向平面通过栅极NFET提供不同的高k金属栅极堆叠来增加平面栅极NFET的阈值电压，而不是平面下拉NFET。特别地，形成在高k电介质层上的阈值电压调节电介质层保留在平面通过栅极NFET中，并在平面下拉式NFET中去除。用于平面通过栅极NFET和平面下拉NFET的组合NFET有源区域基本上是矩形的，这使得能够通过光刻装置对组合的NFET有源区域的图像进行高保真打印。

97. 发明授权

US07504696B2 CMOS with dual metal gate 有权
标题翻译： CMOS双金属门
公开(公告)号：US07504696B2
公开(公告)日：2009-03-17
申请号：US11306748
申请日：2006-01-10
申请人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
发明人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823857 , H01L21/823878
摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.
摘要翻译：本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

98. 发明授权

US07439128B2 Method of creating deep trench capacitor using a P+ metal electrode 有权
标题翻译：使用P +金属电极制造深沟槽电容器的方法
公开(公告)号：US07439128B2
公开(公告)日：2008-10-21
申请号：US11124324
申请日：2005-05-06
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Dae-Gyu Park
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Dae-Gyu Park
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译：本发明包括一种方法，包括提供基底的步骤; 在基板中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。

99. 发明申请

US20070278590A1 CMOS WITH DUAL METAL GATE 有权
标题翻译： CMOS双金属门
公开(公告)号：US20070278590A1
公开(公告)日：2007-12-06
申请号：US11306748
申请日：2006-01-10
申请人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
发明人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823857 , H01L21/823878
摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.
摘要翻译：本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

100. 发明申请

US20070262348A1 HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE 失效
标题翻译：具有金属电极的高温稳定的门结构
公开(公告)号：US20070262348A1
公开(公告)日：2007-11-15
申请号：US11782351
申请日：2007-07-24
申请人： Dae-Gyu Park , Oleg Gluschenkov , Michael Gribelyuk , Kwong Wong
发明人： Dae-Gyu Park , Oleg Gluschenkov , Michael Gribelyuk , Kwong Wong
IPC分类号： H01L21/3205 , H01L29/73
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.
摘要翻译：本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式