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1. 发明申请

US20080173946A1 CMOS STRUCTURE INCLUDING DUAL METAL CONTAINING COMPOSITE GATES 有权
标题翻译： CMOS结构包括双金属复合栅
公开(公告)号：US20080173946A1
公开(公告)日：2008-07-24
申请号：US11625984
申请日：2007-01-23
申请人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
发明人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials. The second silicon containing material layer and the second semiconductor substrate region also comprise different materials.
摘要翻译： CMOS结构和制造CMOS结构的方法包括位于具有第一极性的第一半导体衬底区域内的第一晶体管。第一晶体管包括第一栅电极，其包括第一含金属材料层和位于第一含金属材料层上的第一含硅材料层。 CMOS结构还包括位于横向分离的第二半导体衬底区域内的第二晶体管，其具有与第一极性不同的第二极性。第二晶体管包括第二栅电极，第二栅电极包括不同于第一含金属材料层和位于第二含金属材料层上的第二含硅材料层。第一含硅材料层和第一半导体衬底区域包括不同的材料。第二含硅材料层和第二半导体衬底区域也包括不同的材料。

2. 发明授权

US07666774B2 CMOS structure including dual metal containing composite gates 有权
标题翻译： CMOS结构包括双金属复合栅极
公开(公告)号：US07666774B2
公开(公告)日：2010-02-23
申请号：US11625984
申请日：2007-01-23
申请人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
发明人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity. The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials. The second silicon containing material layer and the second semiconductor substrate region also comprise different materials.
摘要翻译： CMOS结构和制造CMOS结构的方法包括位于具有第一极性的第一半导体衬底区域内的第一晶体管。第一晶体管包括第一栅电极，其包括第一含金属材料层和位于第一含金属材料层上的第一含硅材料层。 CMOS结构还包括位于横向分离的第二半导体衬底区域内的第二晶体管，其具有不同于第一极性的第二极性。第二晶体管包括第二栅极电极，其包括与第一含金属材料层不同的组成的第二金属含有材料层和位于第二含金属材料层上的第二含硅材料层。第一含硅材料层和第一半导体衬底区域包括不同的材料。第二含硅材料层和第二半导体衬底区域也包括不同的材料。

3. 发明授权

US07504696B2 CMOS with dual metal gate 有权
标题翻译： CMOS双金属门
公开(公告)号：US07504696B2
公开(公告)日：2009-03-17
申请号：US11306748
申请日：2006-01-10
申请人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
发明人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823857 , H01L21/823878
摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.
摘要翻译：本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

4. 发明申请

US20070278590A1 CMOS WITH DUAL METAL GATE 有权
标题翻译： CMOS双金属门
公开(公告)号：US20070278590A1
公开(公告)日：2007-12-06
申请号：US11306748
申请日：2006-01-10
申请人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
发明人： Huilong Zhu , Zhijiong Luo , Dae-Gyu Park
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823857 , H01L21/823878
摘要： Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second transistor that includes the second gate, wherein the first gate and the second gate are situated on the same substrate. Furthermore, the first metal produces a first threshold voltage characteristic, wherein the first metal comprises tantalum. The second metal produces a second threshold voltage characteristic that differs from the first threshold voltage characteristic, wherein the second metal comprises tungsten.
摘要翻译：本文的实施例提供了制造具有双金属栅极的CMOS的结构和方法。具体地，CMOS包括包括第一金属的第一栅极和包括第二金属的第二栅极。第一栅极包括与包括第二栅极的第二晶体管互补的第一晶体管的一部分，其中第一栅极和第二栅极位于相同的衬底上。此外，第一金属产生第一阈值电压特性，其中第一金属包括钽。第二金属产生与第一阈值电压特性不同的第二阈值电压特性，其中第二金属包括钨。

5. 发明授权

US08643061B2 Structure of high-K metal gate semiconductor transistor 有权
标题翻译：高K金属栅半导体晶体管的结构
公开(公告)号：US08643061B2
公开(公告)日：2014-02-04
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

6. 发明申请

US20120098067A1 STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：高K金属栅极半导体晶体管的结构
公开(公告)号：US20120098067A1
公开(公告)日：2012-04-26
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

7. 发明授权

US08557652B2 Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 失效
公开(公告)号：US08557652B2
公开(公告)日：2013-10-15
申请号：US13608422
申请日：2012-09-10
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

8. 发明申请

US20130019944A1 METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS 有权
公开(公告)号：US20130019944A1
公开(公告)日：2013-01-24
申请号：US13188214
申请日：2011-07-21
申请人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0376
CPC分类号： H01L31/03762 , H01L31/02167 , H01L31/075 , H01L31/1864 , H01L31/202 , Y02E10/548 , Y02P70/521
摘要： A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

9. 发明申请

US20120187502A1 APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS 有权
标题翻译：聚束光束植入用于制造阈值电压调节FET的应用
公开(公告)号：US20120187502A1
公开(公告)日：2012-07-26
申请号：US13432716
申请日：2012-03-28
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
摘要翻译：提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从聚束束植入步骤后的结构。

10. 发明授权

US08030716B2 Self-aligned CMOS structure with dual workfunction 有权
标题翻译：具有双功能功能的自对准CMOS结构
公开(公告)号：US08030716B2
公开(公告)日：2011-10-04
申请号：US12883874
申请日：2010-09-16
申请人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
摘要翻译：公开了一种用于制造CMOS结构的方法。该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。之后是在NFET器件和PFET器件上的Al层的覆盖布置。该方法还包括在Al层上共享的栅极金属层的布置布置。当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

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