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91. 发明授权

US07293158B2 Systems and methods for implementing counters in a network processor with cost effective memory 失效
标题翻译：在具有成本效益的存储器的网络处理器中实现计数器的系统和方法
公开(公告)号：US07293158B2
公开(公告)日：2007-11-06
申请号：US11070060
申请日：2005-03-02
申请人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译：公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。在R-M-W周期的写周期期间，递增的值被写入存储器。写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

92. 发明授权

US07167471B2 Network processor with single interface supporting tree search engine and CAM 失效
标题翻译：具有单界面支持树搜索引擎和CAM的网络处理器
公开(公告)号：US07167471B2
公开(公告)日：2007-01-23
申请号：US09940758
申请日：2001-08-28
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Michael Steven Siegel
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , G11C15/00 , H04L45/745 , H04L45/7453 , H04L49/90
摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.
摘要翻译：一种用于识别与数据包相关联的数据结构的方法和系统。分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。根据寄存器中的表定义，内部处理器可以作出这样的确定。

93. 发明授权

US07161961B2 STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 失效
标题翻译： STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能
公开(公告)号：US07161961B2
公开(公告)日：2007-01-09
申请号：US09880450
申请日：2001-06-13
申请人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
发明人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
IPC分类号： H04J3/00 , H04J3/02 , H04L12/56
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

94. 发明授权

US07149212B2 Apparatus, method and limited set of messages to transmit data between scheduler and a network processor 失效
公开(公告)号：US07149212B2
公开(公告)日：2006-12-12
申请号：US10095844
申请日：2002-03-12
申请人： Jean Louis Calvignac , Marco Heddes , Joseph Franklin Logan
发明人： Jean Louis Calvignac , Marco Heddes , Joseph Franklin Logan
IPC分类号： H04L12/50
CPC分类号： H04L49/9063 , H04L29/06 , H04L49/90 , H04L49/901 , H04L69/12 , H04L69/22
摘要： An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.

95. 发明授权

US07133942B2 Sequence-preserving multiprocessing system with multimode TDM buffer 失效
公开(公告)号：US07133942B2
公开(公告)日：2006-11-07
申请号：US10017171
申请日：2001-12-07
申请人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
IPC分类号： G06F13/00 , G06F13/14 , G08C15/00 , H04J3/22
CPC分类号： G06F15/8053
摘要： A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

96. 发明授权

US07085850B2 Stateless message processing scheme for network processors interactions 失效
公开(公告)号：US07085850B2
公开(公告)日：2006-08-01
申请号：US09934886
申请日：2001-08-22
申请人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
IPC分类号： G06F15/16
CPC分类号： H04L29/06 , H04L69/22
摘要： A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

97. 发明授权

US08130792B2 STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 有权
标题翻译： STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能
公开(公告)号：US08130792B2
公开(公告)日：2012-03-06
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
发明人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
IPC分类号： H04J3/00 , H04J3/02
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

98. 发明授权

US07826486B2 Selective header field dispatch in a network processing system 有权
标题翻译：网络处理系统中的选择性报头字段调度
公开(公告)号：US07826486B2
公开(公告)日：2010-11-02
申请号：US12144195
申请日：2008-06-23
申请人： Jean Louis Calvignac , Gordon Taylor Davis
发明人： Jean Louis Calvignac , Gordon Taylor Davis
IPC分类号： H04J3/24 , H04L12/28
CPC分类号： H04L49/602 , H04L49/354 , H04L49/604 , H04L69/22
摘要： A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.
摘要翻译：公开了一种用于将适当数据发送到网络处理系统的方法和结构，该网络处理系统包括用于提取网络处理器使用的协议报头字段的改进技术。该技术包括根据分组中存在的协议报头的类型对分组的基本分类。根据分类结果，从相应的标题中提取特定参数字段。来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。多个这样的分派消息被捆绑成单个复合调度消息。因此，来自N个分组的所选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以指导入队，在N个数据包的束上进行帧改变。

99. 发明授权

US07474662B2 Systems and methods for rate-limited weighted best effort scheduling 失效
标题翻译：速率限制加权最佳努力调度的系统和方法
公开(公告)号：US07474662B2
公开(公告)日：2009-01-06
申请号：US11119329
申请日：2005-04-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。多个不同流中的每一个都具有相关联的调度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

100. 发明申请

US20080147995A1 SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
标题翻译：多框控制块的系统和方法
公开(公告)号：US20080147995A1
公开(公告)日：2008-06-19
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

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