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1. 发明授权

US08130792B2 STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 有权
标题翻译： STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能
公开(公告)号：US08130792B2
公开(公告)日：2012-03-06
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
发明人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
IPC分类号： H04J3/00 , H04J3/02
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

2. 发明授权

US07161961B2 STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 失效
标题翻译： STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能
公开(公告)号：US07161961B2
公开(公告)日：2007-01-09
申请号：US09880450
申请日：2001-06-13
申请人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
发明人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
IPC分类号： H04J3/00 , H04J3/02 , H04L12/56
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

3. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

4. 发明授权

US07904617B2 Indicating data buffer by last bit flag 失效
标题翻译：用最后一位标志指示数据缓冲区
公开(公告)号：US07904617B2
公开(公告)日：2011-03-08
申请号：US12100739
申请日：2008-04-10
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。最后一位的位置被传送到指示特定帧的结束的网络处理器。

5. 发明授权

US07620048B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07620048B2
公开(公告)日：2009-11-17
申请号：US11152419
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
摘要翻译：公开了用于在通信系统中传送控制信息的装置。该装置包括网络处理器，可操作地耦合到网络处理器的控制点处理器以及由控制点处理器生成的引导帧。引导帧包括其中放置帧控制信息的第一部分，并且被网络处理器用于更新网络处理器内的至少一个控制寄存器; 第二部分，承载由控制点处理器分配的相关器，以将引导的帧响应与其请求相关联; 第三部分承载一个或一系列指导命令; 和一个结束分隔符引导命令。

6. 发明授权

US07590057B2 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07590057B2
公开(公告)日：2009-09-15
申请号：US11152453
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.
摘要翻译：控制子系统，多个接口处理器，多个媒体接口，多个队列可操作地耦合并且响应于控制信号将数据从存储器移动到多个队列中的所选择的一个队列。

7. 发明授权

US07257616B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07257616B2
公开(公告)日：2007-08-14
申请号：US11152119
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

8. 发明授权

US07123622B2 Method and system for network processor scheduling based on service levels 失效
公开(公告)号：US07123622B2
公开(公告)日：2006-10-17
申请号：US09834141
申请日：2001-04-12
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/32 , H04L47/20 , H04L47/2441 , H04L47/28 , H04L47/36 , H04L47/50 , H04L47/58 , H04L47/60 , H04L47/62 , H04L47/623
摘要： A system and method of moving information units from an output flow control toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on a weighted fair queue where position in the queue is adjusted after each service based on a weight factor and the length of frame, a process which provides a method for and system of interaction between different calendar types is used to provide minimum bandwidth, best effort bandwidth, weighted fair queuing service, best effort peak bandwidth, and maximum burst size specifications. The present invention permits different combinations of service that can be used to create different QoS specifications. The “base” services which are offered to a customer in the example described in this patent application are minimum bandwidth, best effort, peak and maximum burst size (or MBS), which may be combined as desired. For example, a user could specify minimum bandwidth plus best effort additional bandwidth and the system would provide this capability by putting the flow queue in both the NLS and WFQ calendar. The system includes tests when a flow queue is in multiple calendars to determine when it must come out.

9. 发明授权

US07072347B2 Assignment of packet descriptor field positions in a network processor 失效
公开(公告)号：US07072347B2
公开(公告)日：2006-07-04
申请号：US09792494
申请日：2001-02-23
申请人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L49/901
摘要： A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

10. 发明授权

US06898179B1 Network processor/software control architecture 失效
标题翻译：网络处理器/软件控制架构
公开(公告)号：US06898179B1
公开(公告)日：2005-05-24
申请号：US09544896
申请日：2000-04-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
IPC分类号： G06F11/00 , H04B7/216 , H04L1/16 , H04L12/26
CPC分类号： G06F15/17
摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.
摘要翻译：提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

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