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91. 发明公开

EP3050112A1 COMPOSITE HIGH-K METAL GATE STACK FOR ENHANCEMENT MODE GAN SEMICONDUCTOR DEVICES 有权转让
标题翻译： ZUSAMMUSTRETZTER HOCH-K-METALL-GATESTAPELFÜRGAN-HALBLEITERBAUELEMENTE MITVERSTÄRKUNGSMODUS
公开(公告)号：EP3050112A1
公开(公告)日：2016-08-03
申请号：EP13894364.2
申请日：2013-09-27
申请人： Intel Corporation
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , CHAU, Robert S. , SUNG, Seung Hoon , GARDNER, Sanaz K.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42392 , H01L21/02178 , H01L21/02181 , H01L21/0254 , H01L21/28264 , H01L29/0673 , H01L29/0847 , H01L29/1054 , H01L29/2003 , H01L29/207 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66484 , H01L29/66522 , H01L29/66742 , H01L29/66795 , H01L29/7831 , H01L29/785 , H01L29/78681 , H01L29/78696
摘要： Enhancement mode gallium nitride (GaN) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (GaN) channel region disposed above a substrate. A gate stack is disposed on the GaN channel region. The gate stack includes a composite gate dielectric layer disposed directly between the GaN channel region and a gate electrode. The composite gate dielectric layer includes a high band gap Group III-N layer, a first high-K dielectric oxide layer, and a second high-K dielectric oxide layer having a higher dielectric constant than the first high-K dielectric oxide layer. Source/drain regions are disposed on either side of the GaN channel region.
摘要翻译：描述了具有复合高k金属栅极叠层的增强模式氮化镓（GaN）半导体器件及其制造方法。在一个示例中，半导体器件包括设置在衬底上方的氮化镓（GaN）沟道区。栅叠层设置在GaN沟道区上。栅极堆叠包括直接设置在GaN沟道区和栅电极之间的复合栅介质层。复合栅极电介质层包括具有比第一高K电介质氧化物层更高的介电常数的高带隙组III-N层，第一高K电介质氧化物层和第二高K电介质氧化物层。源极/漏极区域设置在GaN沟道区域的两侧。

92. 发明公开

EP2901484A1 SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS&ENHANCEMENT MODE OPERATION 审中-公开
标题翻译：自对准结构和方法，增益模式不对称的晶体管和GAN-OPERATION
公开(公告)号：EP2901484A1
公开(公告)日：2015-08-05
申请号：EP13841467.7
申请日：2013-06-12
申请人： Intel Corporation
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , MUKHERJEE, Niloy , GOEL, Niti , KABEHIE, Sanaz , SUNG, Seung Hoon , PILLARISETTY, Ravi , CHAU, Robert S.
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
摘要翻译：实施例包括高电子迁移率晶体管（HEMT）。在实施例中，栅电极被从源间隔开不同的距离和漏半导体区域，以提供高击穿电压和低导通状态电阻。在实施例中，自对准技术应用于以形成沟槽和到中间芯棒unabhängig限定与单个掩蔽操作的栅极长度，栅极 - 源极长度，栅极 - 漏极长度的电介质衬垫。在实施方案中，III-N HEMT器件包括用于阈值电压调节和/或增强模式操作氟掺杂的半导体势垒层。

93. 发明公开

EP2659514A2 A METHOD TO REDUCE CONTACT RESISTANCE OF N-CHANNEL TRANSISTORS BY USING A III-V SEMICONDUCTOR INTERLAYER IN SOURCE AND DRAIN 有权
标题翻译：一种用于减少N沟道晶体管的接触电阻USING A III-V族半导体移位之间在源和谷
公开(公告)号：EP2659514A2
公开(公告)日：2013-11-06
申请号：EP11854145.7
申请日：2011-12-20
申请人： Intel Corporation
发明人： MUKHERJEE, Niloy , DEWEY, Gilbert , RADOSAVLJEVIC, Marko , CHAU, Robert S. , METZ, Matthew V.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28575 , H01L29/66446
摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

94. 发明公开

EP4218054A1 GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY 审中-实审
公开(公告)号：EP4218054A1
公开(公告)日：2023-08-02
申请号：EP21873162.8
申请日：2021-08-26
申请人： INTEL Corporation
发明人： THEN, Han Wui , RADOSAVLJEVIC, Marko , KOIRALA, Pratik , THOMAS, Nicole K. , FISCHER, Paul B. , ELSHERBINI, Adel A. , TALUKDAR, Tushar , SWAN, Johanna M. , GOMES, Wilfred , CHAU, Robert S. , CHOI, Beomseok
IPC分类号： H01L27/06 , H01L29/20 , H01L27/092 , H01L21/8238

95. 发明公开

EP3329515A1 FUNCTIONAL METAL OXIDE BASED MICROELECTRONIC DEVICES 审中-公开
公开(公告)号：EP3329515A1
公开(公告)日：2018-06-06
申请号：EP15900522.2
申请日：2015-07-31
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , MAJHI, Prashant , KOTLYAR, Roza , MUKHERJEE, Niloy , KUO, Charles C. , SHAH, Uday , PILLARISETTY, Ravi , CHAU, Robert S.
IPC分类号： H01L29/02
CPC分类号： H01L29/7869 , H01L27/0705 , H01L27/1225 , H01L29/02 , H01L29/4908 , H01L29/78603 , H01L29/78642
摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

96. 发明公开

EP3298628A1 SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE STRUCTURES 审中-公开
标题翻译：半导体器件与提高掺杂晶体结构
公开(公告)号：EP3298628A1
公开(公告)日：2018-03-28
申请号：EP15892756.6
申请日：2015-05-19
申请人： INTEL Corporation
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , GARDNER, Sanaz K. , SUNG, Seung Hoon , THEN, Han Wui , CHAU, Robert S.
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L21/02381 , H01L21/02488 , H01L21/02513 , H01L21/0254 , H01L21/02647 , H01L21/823431 , H01L21/8252 , H01L21/8258 , H01L29/0657 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/205 , H01L29/66462
摘要： Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

97. 发明公开

EP3235008A1 INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE STRUCTURES AND METHODS ASSOCIATED THEREWITH 审中-公开
标题翻译：具有减少的缺陷III族氮化物结构的集成电路裸片及与其相关的方法
公开(公告)号：EP3235008A1
公开(公告)日：2017-10-25
申请号：EP14908580.5
申请日：2014-12-17
申请人： Intel Corporation
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , GARDNER, Sanaz K. , SUNG, Seung Hoon , CHAU, Robert S. , PILLARISETTY, Ravi
IPC分类号： H01L29/78 , H01L21/318 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L33/007 , H01L33/08 , H01L33/10 , H01L33/12 , H01L33/24 , H01L33/32 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对集成电路（IC）管芯。在实施例中，IC管芯可以包括半导体衬底和设置在半导体衬底之上的缓冲层。缓冲层可以具有形成在其中的多个开口。在实施例中，IC管芯可以进一步包括多个III族氮化物结构。多个III族氮化物结构中的单个III族氮化物结构可以包括设置在多个开口的相应开口中的下部和设置在相应开口上的上部。在实施例中，上部可以包括在缓冲层的表面上从相应开口的侧壁径向延伸的基部，以形成围绕相应开口的周边。其他实施例可以被描述和/或要求保护。

98. 发明公开

EP3234996A1 INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE LAYER AND METHODS ASSOCIATED THEREWITH 审中-公开
标题翻译：具有减少的缺陷III族氮化物层的集成电路裸片及与其相关的方法
公开(公告)号：EP3234996A1
公开(公告)日：2017-10-25
申请号：EP14908583.9
申请日：2014-12-17
申请人： Intel Corporation
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , CHAU, Robert S. , GARDNER, Sanaz K. , SUNG, Seung Hoon
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L21/0265 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02551 , H01L21/02554 , H01L21/02557 , H01L21/0256 , H01L21/02562 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0274 , H01L21/8258 , H01L23/48 , H01L24/16 , H01L25/065 , H01L27/0605 , H01L27/092 , H01L27/0922 , H01L29/0657 , H01L29/0688 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/2203 , H01L29/225 , H01L29/267 , H01L29/32 , H01L29/66462 , H01L29/66969 , H01L29/7786 , H01L2224/16227 , H01L2924/15311
摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对集成电路（IC）管芯。在实施例中，IC管芯可以包括半导体衬底，设置在半导体衬底上的III族氮化物或II-VI纤锌矿层以及至少部分地嵌入III族氮化物或II-VI纤锌矿中的多个缓冲结构层。在一些实施例中，多个缓冲结构中的每一个可以包括设置在半导体衬底上方的中央构件，设置在半导体衬底上方并且远离中央构件侧向延伸的下侧向构件以及设置在中央构件上方的上侧向构件并且从中央构件沿与下侧部件相反的方向横向延伸。多个缓冲结构可以交错布置来定位以终止III族氮化物或II-VI纤锌矿层的缺陷。其他实施例可以被描述和/或要求保护。

99. 发明公开

EP3198645A1 1S1R MEMORY CELLS INCORPORATING A BARRIER LAYER 审中-公开
标题翻译： 1S1R内存单元包含一个屏障层
公开(公告)号：EP3198645A1
公开(公告)日：2017-08-02
申请号：EP14902489.5
申请日：2014-09-25
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , MUKHERJEE, Niloy , MAJHI, Prashant , CHAU, Robert S.
IPC分类号： H01L27/115 , H01L27/11502
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/147 , H01L45/16
摘要： Thin film 1S1R bitcells incorporating a barrier between selector and memory elements. Devices incorporating such bitcells and methods of forming such bitcells are also described. In embodiments, the selector and memory element is each a dielectric material, and advantageously a metal oxide. Between the selector and memory elements is a barrier, which is to reduce intermixing and/or reaction of selector material and memory material. Addition of a barrier layer having suitable material properties into the 1S1R stack may extend the operating lifetime of a bitcell incorporated the stack by resisting intermixing and/or reaction of the selector and memory thin film materials driven by thermal and/or electric field stresses experienced by a bitcell during operation. In embodiments, a barrier layer may include one or more material layers having a composition distinct from the material composition(s) of the selector and memory elements.
摘要翻译：薄膜1S1R位单元在选择器和存储器元件之间包含屏障。还描述了包含这种位单元的器件以及形成这种位单元的方法。在实施例中，选择器和存储器元件各自是电介质材料，并且有利地是金属氧化物。在选择器和存储器元件之间是屏障，其用于减少选择器材料和存储器材料的混合和/或反应。向1S1R叠层中添加具有合适材料特性的阻挡层可以通过抵抗选择器和存储器薄膜材料的混合和/或反应来延长并入叠层中的位单元的工作寿命，所述选择器和存储器薄膜材料由操作过程中的位单元。在实施例中，阻挡层可以包括具有与选择器和存储器元件的材料组成不同的组成的一个或多个材料层。

100. 发明公开

EP3198601A1 AMORPHOUS SEED LAYER FOR IMPROVED STABILITY IN PERPENDICULAR STTM STACK 审中-公开
标题翻译：用于改善垂直STTM叠层稳定性的非晶种子层
公开(公告)号：EP3198601A1
公开(公告)日：2017-08-02
申请号：EP14902854.0
申请日：2014-09-26
申请人： INTEL Corporation
发明人： DOCZY, Mark L. , OGUZ, Kaan , DOYLE, Brian S. , KUO, Charles C. , CHAU, Robert S. , SURI, Satyarth
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , H01F10/3286 , H01L27/222 , H01L43/10 , H01L43/12
摘要： A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.
摘要翻译：一种用于磁隧道结的材料层堆叠，所述材料层堆叠包括固定磁层; 介电层; 自由磁层; 和无定形导电晶种层，其中所述固定磁性层设置在所述介电层和所述晶种层之间。一种非易失性存储器件，包括：包括非晶导电籽晶层的材料堆叠; 以及与种子层并列并接触的固定磁性层。一种方法，包括：在存储器件的第一电极上形成无定形种子层; 在所述非晶种子层上形成材料层堆叠，所述材料堆叠包括布置在固定磁性层与自由磁性层之间的介电层，其中所述固定磁性层。

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