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1. 发明公开

EP4156232A1 MEMORY DEVICES WITH NITRIDE-BASED FERROELECTRIC MATERIALS 审中-实审
公开(公告)号：EP4156232A1
公开(公告)日：2023-03-29
申请号：EP22190629.0
申请日：2022-08-16
申请人： INTEL Corporation
发明人： KARPOV, Elijah V. , AVCI, Uygar E. , SHIVARAMAN, Shriram , CHANG, Sou-Chi
IPC分类号： H01L21/28 , H10B53/30
摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices (100) comprising a plateline (102), a node (110) and a capacitor (120) coupled to the plateline, wherein the capacitor comprises a nitride-base ferroelectric material (112), for example aluminum scandium nitride AlScN.

2. 发明公开

EP4163968A1 CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT TAPS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-实审
公开(公告)号：EP4163968A1
公开(公告)日：2023-04-12
申请号：EP22205431.4
申请日：2022-09-22
申请人： Intel Corporation
发明人： CHANDHOK, Manish , KARPOV, Elijah V. , HARAN, Mohit , PATEL, Reken , WALLACE, Charles H. , SINGH, Gurpreet , GSTREIN, Florian , HAN, Eungnak , ALAAN, Urusa , GULER, Leonard P. , NYHUS, Paul A.
IPC分类号： H01L23/528 , H01L29/78 , H01L23/485 , H01L21/768 , H01L23/532
摘要： Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

3. 发明公开

EP3329515A1 FUNCTIONAL METAL OXIDE BASED MICROELECTRONIC DEVICES 审中-公开
公开(公告)号：EP3329515A1
公开(公告)日：2018-06-06
申请号：EP15900522.2
申请日：2015-07-31
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , MAJHI, Prashant , KOTLYAR, Roza , MUKHERJEE, Niloy , KUO, Charles C. , SHAH, Uday , PILLARISETTY, Ravi , CHAU, Robert S.
IPC分类号： H01L29/02
CPC分类号： H01L29/7869 , H01L27/0705 , H01L27/1225 , H01L29/02 , H01L29/4908 , H01L29/78603 , H01L29/78642
摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

4. 发明公开

EP3198645A1 1S1R MEMORY CELLS INCORPORATING A BARRIER LAYER 审中-公开
标题翻译： 1S1R内存单元包含一个屏障层
公开(公告)号：EP3198645A1
公开(公告)日：2017-08-02
申请号：EP14902489.5
申请日：2014-09-25
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , MUKHERJEE, Niloy , MAJHI, Prashant , CHAU, Robert S.
IPC分类号： H01L27/115 , H01L27/11502
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/147 , H01L45/16
摘要： Thin film 1S1R bitcells incorporating a barrier between selector and memory elements. Devices incorporating such bitcells and methods of forming such bitcells are also described. In embodiments, the selector and memory element is each a dielectric material, and advantageously a metal oxide. Between the selector and memory elements is a barrier, which is to reduce intermixing and/or reaction of selector material and memory material. Addition of a barrier layer having suitable material properties into the 1S1R stack may extend the operating lifetime of a bitcell incorporated the stack by resisting intermixing and/or reaction of the selector and memory thin film materials driven by thermal and/or electric field stresses experienced by a bitcell during operation. In embodiments, a barrier layer may include one or more material layers having a composition distinct from the material composition(s) of the selector and memory elements.
摘要翻译：薄膜1S1R位单元在选择器和存储器元件之间包含屏障。还描述了包含这种位单元的器件以及形成这种位单元的方法。在实施例中，选择器和存储器元件各自是电介质材料，并且有利地是金属氧化物。在选择器和存储器元件之间是屏障，其用于减少选择器材料和存储器材料的混合和/或反应。向1S1R叠层中添加具有合适材料特性的阻挡层可以通过抵抗选择器和存储器薄膜材料的混合和/或反应来延长并入叠层中的位单元的工作寿命，所述选择器和存储器薄膜材料由操作过程中的位单元。在实施例中，阻挡层可以包括具有与选择器和存储器元件的材料组成不同的组成的一个或多个材料层。

5. 发明公开

EP4290565A1 SELF-ALIGNED STAGGERED INTEGRATED CIRCUIT INTERCONNECT FEATURES 审中-实审
公开(公告)号：EP4290565A1
公开(公告)日：2023-12-13
申请号：EP23171920.4
申请日：2023-05-05
申请人： Intel Corporation
发明人： RESHOTKO, Miriam , KARPOV, Elijah V. , ANDERS, Mark A. , AULUCK, Gauri , SUNDARARAJAN, Shakuntala , Makowski, Michael , BARRETT, Caleb
IPC分类号： H01L21/768 , H01L23/528 , H01L23/522
摘要： Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

6. 发明公开

EP4106006A1 TRANSISTORS WITH FERROELECTRIC GATES 审中-实审
公开(公告)号：EP4106006A1
公开(公告)日：2022-12-21
申请号：EP22183478.1
申请日：2019-06-25
申请人： INTEL Corporation
发明人： SHARMA, Abhishek Anil , PILLARISETTY, Ravi , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant , DEWEY, Gilbert W. , CHU-KUNG, Benjamin , LE, Van H. , KAVALIEROS, Jack T. , GHANI, Tahir
IPC分类号： H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786
摘要： An integrated circuit (IC) structure comprises a transistor including a channel material, and a gate stack, including a gate electrode material, and a material between the gate electrode material and the channel material, wherein at least 20% of crystals of the material are arranged in an orthorhombic crystal lattice.

7. 发明公开

EP3685443A1 STRAINED THIN FILM TRANSISTORS 审中-实审
公开(公告)号：EP3685443A1
公开(公告)日：2020-07-29
申请号：EP17925227.5
申请日：2017-09-18
申请人： INTEL Corporation
发明人： MAJHI, Prashant , RACHMADY, Willy , DOYLE, Brian S. , SHARMA, Abhishek A. , KARPOV, Elijah V. , PILLARISETTY, Ravi , KAVALIEROS, Jack T.
IPC分类号： H01L29/786

8. 发明公开

EP3221892A1 RARE EARTH METAL&METAL OXIDE ELECTRODE INTERFACING OF OXIDE MEMORY ELEMENT IN RESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：氧化物半导体存储器元件在抗阻存储单元中的稀土金属与金属氧化物电极的界面
公开(公告)号：EP3221892A1
公开(公告)日：2017-09-27
申请号：EP14902379.8
申请日：2014-09-25
申请人： Intel Corporation
发明人： MAJHI, Prashant , KARPOV, Elijah V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , SHAH, Uday , DOYLE, Brian S. , CHAU, Robert S.
IPC分类号： H01L27/115
CPC分类号： H01L45/146 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/16
摘要： Thin film resistive memory material stacks including at least one of a high work function metal oxide at an interface of a first electrode and a thin film memory material, and a low work function rare earth metal at an interface of a second electrode and the thin film memory material. The high work function metal oxide provides a good Schottky barrier height relative to memory material for high on/off current ratio. Compatibility of the metal oxide with switching oxide reduces cycling loss of oxygen/vacancies for improved memory device durability. The low work function rare earth metal provides high oxygen solubility to enhance vacancy creation within the memory material in as-deposited state for low forming voltage requirements while providing an ohmic contact to the resistive memory material.
摘要翻译：包括在第一电极和薄膜存储材料的界面处的高功函数金属氧化物和在第二电极和薄膜的界面处的低功函数稀土金属中的至少一种的薄膜电阻存储材料堆叠记忆材料。高功函数金属氧化物相对于存储材料提供良好的肖特基势垒高度，以实现高开/关电流比。金属氧化物与开关氧化物的相容性降低了氧/空位的循环损耗，从而提高了存储器件的耐用性。低功函数稀土金属提供高的氧溶解度，以提高存储材料内的存储材料中的空位，以便形成低电压要求，同时为电阻存储材料提供欧姆接触。

9. 发明申请

WO2019066964A1 1S-1C DRAM WITH A NON-VOLATILE CBRAM ELEMENT 审中-公开
公开(公告)号：WO2019066964A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054597
申请日：2017-09-29
申请人： INTEL CORPORATION , PILLARISETTY, Ravi , SHARMA, Abhishek A. , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant
发明人： PILLARISETTY, Ravi , SHARMA, Abhishek A. , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant
IPC分类号： H01L27/108 , H01L27/115
摘要： One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F 2 or less density.

10. 发明申请

WO2019055003A1 SELECTOR ELEMENT WITH BALLAST FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES 审中-公开
公开(公告)号：WO2019055003A1
公开(公告)日：2019-03-21
申请号：PCT/US2017/051367
申请日：2017-09-13
申请人： INTEL CORPORATION , MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , DOYLE, Brian S. , SHARMA, Abhishek A.
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , DOYLE, Brian S. , SHARMA, Abhishek A.
IPC分类号： H01L45/00 , H01L43/02
CPC分类号： H01L27/2409 , H01L27/224 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

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