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91. 发明申请

US20090033876A1 ILLUMINATOR AND PROJECTION DISPLAY EMPLOYING IT 审中-公开
标题翻译：照明器和投影显示器使用它
公开(公告)号：US20090033876A1
公开(公告)日：2009-02-05
申请号：US11912590
申请日：2006-07-25
申请人： Yusaku Shimaoka , Atsushi Hatakeyama
发明人： Yusaku Shimaoka , Atsushi Hatakeyama
IPC分类号： G03B21/14 , G02B27/10
CPC分类号： G03B21/2033 , G03B33/06 , H04N9/3111 , H04N9/3164
摘要： An illuminator includes a color composition prism (24) consisting of first to third prisms (21-23), a red light emitting diode (1), a blue light emitting diode (2) and a green light emitting diode (3) emitting three light beams having different spectrum intervals, a first optical thin film (31) formed on the surface of the first prism (21) opposing the second prism (22) and having a cutoff wavelength between red and green, and a second optical thin film (32) formed on the surface of the second prism (22) opposing the third prism (23) and having a cutoff wavelength between blue and green. Consequently, it is possible to provide an illuminator that can conduct a color composition in which an optical loss at the time of color composition and a color unevenness occurring on the optical thin film due to the incident angle dependency are decreased even for natural light not under a polarization control.
摘要翻译：照明器包括由第一至第三棱镜（21-23），红色发光二极管（1），蓝色发光二极管（2）和绿色发光二极管（3）组成的彩色合成棱镜（24）具有不同光谱间隔的光束，形成在与第二棱镜（22）相对的第一棱镜（21）的表面上并且具有红色和绿色之间的截止波长的第一光学薄膜（31）和第二光学薄膜 32），形成在与第三棱镜（23）相对的第二棱镜（22）的表面上，并具有蓝色和绿色之间的截止波长。因此，可以提供一种可以进行颜色组合的照明器，其中即使对于不在下面的自然光也会导致由于入射角依赖性而在光学薄膜上产生的光学损失和光学薄膜上出现的颜色不均匀的颜色组合极化控制。

92. 发明授权

US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
标题翻译：配有参考电池和负载平衡电路的多值非易失性半导体存储器件
公开(公告)号：US07307885B2
公开(公告)日：2007-12-11
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
摘要翻译：非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

93. 发明授权

US07224602B2 Semiconductor memory device and control method having data protection feature 有权
标题翻译：具有数据保护特性的半导体存储器件和控制方法
公开(公告)号：US07224602B2
公开(公告)日：2007-05-29
申请号：US11126869
申请日：2005-05-11
申请人： Kazunari Kido , Minoru Yamashita , Kazuhiro Kurihara , Atsushi Hatakeyama , Hiroaki Wada
发明人： Kazunari Kido , Minoru Yamashita , Kazuhiro Kurihara , Atsushi Hatakeyama , Hiroaki Wada
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/08 , G06F12/1425 , G11C16/22 , Y02D10/13
摘要： A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
摘要翻译：一种半导体器件包括：第一存储单元阵列，其包括用于存储数据的存储器单元，并以扇区为基础进行管理;第二存储单元阵列，包括存储器单元，该存储单元存储基于扇区的扇区保护信息;以及控制电路，检查扇区保护信息每当选择要编程或擦除的扇区时，存储在第二存储单元阵列中。因此，所有扇区中的扇区保护信息在上电时不必被锁存。不必提供与扇区数量相等的锁存电路。因此可以大大减少电路的数量，并且可以减小芯片面积。

94. 发明申请

US20050185465A1 Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：US20050185465A1
公开(公告)日：2005-08-25
申请号：US11110700
申请日：2005-04-21
申请人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C8/12 , G11C11/34 , G11C16/26
CPC分类号： G11C16/26 , G11C8/12
摘要： A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.
摘要翻译：存储器件包括多个存储体（BNKA，BNKB，BNKC和BNKD），并且每个存储体包括存储数据的多个存储单元和从多个存储单元读取数据的多个位线。所有多个组的位线长度相等。

95. 发明申请

US20050141306A1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US20050141306A1
公开(公告)日：2005-06-30
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C5/06 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

96. 发明授权

US06181637B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US06181637B2
公开(公告)日：2001-01-30
申请号：US09523307
申请日：2000-03-10
申请人： Koichi Nishimura , Atsushi Hatakeyama
发明人： Koichi Nishimura , Atsushi Hatakeyama
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： A memory device having memory cells at cross sections of word lines and bit lines, a word-line driver for driving the word lines in response to a first activation signal, a delay circuit for generating a second activation signal that delays the first activation signal, and a sense amp for amplifying the voltage read from the memory cell in response to the second activation signal, comprises: a first power-supply voltage that is supplied to the word-line driver, and a second power-supply voltage that is supplied to the delay circuit, where the second power-supply voltage is generated from the first power-supply voltage. In the present invention, there is a first power-supply voltage that is supplied to the word-line driver, and a second power-supply voltage that is supplied to the delay circuit. And since the second power-supply voltage is generated from the first power-supply voltage, the delay time of the delay circuit is depending on the first power-supply voltage, but does not depend on the external power supply voltage. In addition, the activation timing of the sense amp does not become faster due to fluctuations of the external power-supply voltage, and since it is possible to stably maintain the required WL-LE interval, it is possible to operate the memory properly without an increase in power consumption of the memory device.
摘要翻译：具有在字线和位线的横截面处的存储单元的存储器件，用于响应于第一激活信号驱动字线的字线驱动器，用于产生延迟第一激活信号的第二激活信号的延迟电路，以及用于响应于所述第二激活信号放大从所述存储单元读取的电压的感测放大器，包括：提供给所述字线驱动器的第一电源电压和提供给所述第二电源电压的第二电源电压，延迟电路，其中从第一电源电压产生第二电源电压。在本发明中，存在被提供给字线驱动器的第一电源电压和第二电源电压提供给延迟电路的电压。并且，由于从第一电源电压产生第二电源电压，延迟电路的延迟时间取决于第一电源电压，而是不依赖于外部电源电压。此外，由于外部电源电压的波动，感测放大器的激活定时不会变得更快，并且由于可以稳定地保持所需的WL-LE间隔，所以可以正确地操作存储器，而不需要增加存储设备的功耗。

97. 发明授权

US06042236A Projection type video image display device 失效
标题翻译：投影型视频图像显示装置
公开(公告)号：US06042236A
公开(公告)日：2000-03-28
申请号：US50039
申请日：1998-03-30
申请人： Atsushi Hatakeyama , Shigekazu Yamagishi
发明人： Atsushi Hatakeyama , Shigekazu Yamagishi
IPC分类号： G03B33/12 , G02F1/13 , G02F1/1335 , G02F1/1347 , G03B21/00 , H04N5/74 , H04N9/31 , G03B21/14
CPC分类号： H04N9/3108 , G02B27/102 , G02B27/1046 , G02B27/149 , H04N5/7441
摘要： A light source for emitting a white light in one direction, color light separating means for separating the white light from the light source into three color lights of red light, blue light and green light, modulating means including liquid crystal light valves for modulating the polarized lights contained in the luminous fluxes from the color light separating means, and producing a video image, color light combining means for combining the modulated luminous fluxes after being modulated by the modulating means, and projection optical means for projecting the combined luminous flux obtained by the color light combining means on a screen. A polarizer is disposed at the light exit side of the modulating means. A dichroic filter having characteristics for selectively passing and selectively reflecting the color lights from the modulating means is disposed between the color light combining means and the modulating means positioned on an optical path of at least one color light of the three color lights of the red light, blue light and green light. The quarter-wave plate has a plurality of quarter-wave plates, a first quarter-wave plate of the plurality of quarter-wave plates is contacting with the dichroic filter, and a second quarter-wave plate of the plurality of quarter-wave plates contacts the dichroic filter, and is disposed between the dichroic filter and the color light combining means.
摘要翻译：用于沿一个方向发射白光的光源，用于将来自光源的白光分离成红色光，蓝色光和绿色光的三色光的色光分离装置，包括用于调制偏振光的液晶光阀的调制装置包含在来自彩色光分离装置的光通量中的光，并产生视频图像，用于将由调制装置调制后的调制光束组合的彩色光合成装置和投影光学装置，用于投射由彩色光合成装置在屏幕上。偏振器设置在调制装置的光出射侧。具有用于选择性地通过和选择性地反射来自调制装置的彩色光的特性的二向色滤光器设置在色光合成装置和位于红光三色光的至少一种色光的光路上的调制装置之间，蓝光和绿光。四分之一波片具有多个四分之一波片，多个四分之一波片的第一四分之一波片与二向色滤光片接触，并且多个四分之一波片的第二四分之一波片与二向色滤光片接触，并设置在二向色滤光片和彩色光合成装置之间。

98. 发明授权

US5986960A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5986960A
公开(公告)日：1999-11-16
申请号：US910899
申请日：1997-08-13
申请人： Shinya Fujioka , Atsushi Hatakeyama
发明人： Shinya Fujioka , Atsushi Hatakeyama
IPC分类号： G11C11/413 , G11C5/14 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/409 , H01L27/10 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4082 , G11C11/4087 , G11C8/10 , Y10T307/826
摘要： A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.
摘要翻译：具有DRAM等的半导体集成电路包括包含多个存储单元的存储单元块和用于选择和激活存储单元块内的指定存储单元的核心电路部分，并且构成为步骤在激活状态时，向核心电路部分施加电压。半导体集成电路还包括用于将升压电压降低预定值的升压降压单元和用于选择性地将升压电压和升压降压单元的输出电压提供给芯的单元电路部分

99. 发明授权

US5757691A Semiconductor memory device having wiring for selection of redundant cells but without useless region on chip 失效
标题翻译：半导体存储器件具有用于选择冗余单元但芯片上没有无用区域的布线
公开(公告)号：US5757691A
公开(公告)日：1998-05-26
申请号：US869637
申请日：1997-06-05
申请人： Atsushi Hatakeyama
发明人： Atsushi Hatakeyama
IPC分类号： H01L21/822 , G11C5/06 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/04 , H01L27/10
CPC分类号： G11C29/80 , G11C5/063
摘要： A semiconductor memory device includes: cell arrays each including a normal cell array portion and a redundant cell array portion in which a plurality of normal cells and a plurality of redundant cells are arranged respectively; a first wiring, laid out in a row direction within the redundant cell array portions, for selecting the redundant cells; a second wiring orthogonal to the first wiring and formed on a different wiring layer from the first wiring; a peripheral circuit region; and a redundancy judgment circuit placed in the peripheral circuit region. The first wiring is connected with the second wiring within the cell arrays, and connected to the redundancy judgment circuit by way of the second wiring. Owing to this configuration, the wiring for selecting the redundant cells can be arranged without the need of forming a useless region on a chip. This contributes to the effort to stop the area of a chip from increasing.
摘要翻译：半导体存储器件包括：各自包括正常单元阵列部分和冗余单元阵列部分的单元阵列，其中分别布置多个正常单元和多个冗余单元; 在所述冗余单元阵列部分内沿行方向布置的用于选择所述冗余单元的第一布线; 与所述第一布线正交的第二布线，并形成在与所述第一布线不同的布线层上; 外围电路区域; 以及设置在外围电路区域中的冗余判断电路。第一布线与单元阵列内的第二布线连接，并通过第二布线连接到冗余判断电路。由于这种配置，可以布置用于选择冗余单元的布线，而不需要在芯片上形成无用的区域。这有助于阻止芯片面积的增加。

100. 发明授权

US5745745A Text search method and apparatus for structured documents 失效
标题翻译：文本搜索方法和结构化文档的设备
公开(公告)号：US5745745A
公开(公告)日：1998-04-28
申请号：US495232
申请日：1995-06-27
申请人： Katsumi Tada , Atsushi Hatakeyama , Hisamitsu Kawaguchi , Natsuko Mizutani , Kanji Kato , Satoshi Asakawa
发明人： Katsumi Tada , Atsushi Hatakeyama , Hisamitsu Kawaguchi , Natsuko Mizutani , Kanji Kato , Satoshi Asakawa
IPC分类号： G06F17/30
CPC分类号： G06F17/30911 , G06F2216/11 , Y10S707/99931 , Y10S707/99935 , Y10S707/99936
摘要： A text search method for structured documents and apparatus wherein structured document database to be searched is created by adding logical structure length information to logical structure discriminating information on the basis of a structured document constituted by a plurality of logical structures and logical structure discriminator information, and in searching the structured document database in accordance with an entered search key constituted by a logical structure and a search character string, the search of a logical structure other than the entered logical structure is skipped based upon the data length information. In the method and apparatus, by using a structured document, structured document database to be searched is created which is constituted by a condensed text for each logical structure constituted by a list of words contained in the logical structure, a character occurrence bitmap for each logical structure constituted by a list of characters contained in the logical structure and an source structured document, and then the structured document database is searched in accordance with an entered search key constituted by a logical structure and a search character string. An source structured document is searched optionally depending upon the entered search key.
摘要翻译：用于结构化文档和装置的文本搜索方法，其中通过基于由多个逻辑结构和逻辑结构鉴别器信息构成的结构化文档将逻辑结构长度信息添加到逻辑结构鉴别信息来创建要搜索的结构化文档数据库，以及在根据由逻辑结构和搜索字符串构成的输入的搜索关键字搜索结构化文档数据库时，基于数据长度信息来跳过除输入的逻辑结构之外的逻辑结构的搜索。在该方法和装置中，通过使用结构化文档，创建由被包含在逻辑结构中的单词列表构成的每个逻辑结构的精简文本构成的要搜索的结构化文档数据库，每个逻辑的字符出现位图由包含在逻辑结构中的字符列表和源结构化文档构成的结构，然后根据由逻辑结构和搜索字符串构成的输入搜索关键字搜索结构化文档数据库。根据输入的搜索关键字可选地搜索源结构化文档。

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