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1. 发明授权

US5986960A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5986960A
公开(公告)日：1999-11-16
申请号：US910899
申请日：1997-08-13
申请人： Shinya Fujioka , Atsushi Hatakeyama
发明人： Shinya Fujioka , Atsushi Hatakeyama
IPC分类号： G11C11/413 , G11C5/14 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/409 , H01L27/10 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4082 , G11C11/4087 , G11C8/10 , Y10T307/826
摘要： A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.
摘要翻译：具有DRAM等的半导体集成电路包括包含多个存储单元的存储单元块和用于选择和激活存储单元块内的指定存储单元的核心电路部分，并且构成为步骤在激活状态时，向核心电路部分施加电压。半导体集成电路还包括用于将升压电压降低预定值的升压降压单元和用于选择性地将升压电压和升压降压单元的输出电压提供给芯的单元电路部分

2. 发明授权

US5668763A Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks 失效
标题翻译：半导体存储器，用于通过选择和使用良好的存储器块来增加半个好的存储器的数量
公开(公告)号：US5668763A
公开(公告)日：1997-09-16
申请号：US606819
申请日：1996-02-26
申请人： Shinya Fujioka , Atsushi Hatakeyama , Hirohiko Mochizuki
发明人： Shinya Fujioka , Atsushi Hatakeyama , Hirohiko Mochizuki
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A semiconductor memory has a plurality of memory arrays, and a plurality of selection circuits. Each of the memory arrays has a plurality of memory blocks. The selection circuits is provided to the memory arrays and is used to independently disable a defective memory block and select a normal memory block in the memory array. Therefore, the semiconductor memory enables to increase the number of partial good memories (half good memories: half capacity memory), and to increase a product yield.
摘要翻译：半导体存储器具有多个存储器阵列和多个选择电路。每个存储器阵列具有多个存储器块。选择电路被提供给存储器阵列，并且用于独立地禁用缺陷存储器块并选择存储器阵列中的正常存储器块。因此，半导体存储器能够增加部分良好存储器的数量（半好的存储器：半容量存储器），并且增加产品产量。

3. 发明授权

US07903487B2 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US07903487B2
公开(公告)日：2011-03-08
申请号：US12201922
申请日：2008-08-29
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

4. 发明授权

US07869296B2 Semiconductor memory device, and method of controlling the same 有权
公开(公告)号：US07869296B2
公开(公告)日：2011-01-11
申请号：US11515852
申请日：2006-09-06
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

5. 发明授权

US07848176B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07848176B2
公开(公告)日：2010-12-07
申请号：US12428828
申请日：2009-04-23
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

6. 发明授权

US07778099B2 Semiconductor memory, memory system, and memory access control method 有权
标题翻译：半导体存储器，存储器系统和存储器访问控制方法
公开(公告)号：US07778099B2
公开(公告)日：2010-08-17
申请号：US12258970
申请日：2008-10-27
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.
摘要翻译：提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。

7. 发明授权

US07730232B2 Data transfer method and system 失效
标题翻译：数据传输方式和系统
公开(公告)号：US07730232B2
公开(公告)日：2010-06-01
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译：提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从响应于确认完成数据传送的传送状态。

8. 发明授权

US07200059B2 Semiconductor memory and burn-in test method of semiconductor memory 有权
标题翻译：半导体存储器的半导体存储器和老化测试方法
公开(公告)号：US07200059B2
公开(公告)日：2007-04-03
申请号：US11260486
申请日：2005-10-28
申请人： Shinya Fujioka , Yoshiaki Okuyama , Yasuhiro Takada , Tatsuhiro Watanabe , Nobumi Kodama
发明人： Shinya Fujioka , Yoshiaki Okuyama , Yasuhiro Takada , Tatsuhiro Watanabe , Nobumi Kodama
IPC分类号： G11C29/00
CPC分类号： G11C29/06 , G11C29/10 , G11C2029/0405 , G11C2029/1204 , G11C2029/3602
摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.
摘要翻译：包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线对，其中位线彼此平行的非扭转结构。由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。可以防止记忆单元的特性从老化测试过度恶化。此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。因此，可以降低测试成本。

9. 发明申请

US20070014178A1 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20070014178A1
公开(公告)日：2007-01-18
申请号：US11515853
申请日：2006-09-06
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C5/14 , G11C7/00 , G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

10. 发明申请

US20050259492A1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US20050259492A1
公开(公告)日：2005-11-24
申请号：US11024737
申请日：2004-12-30
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C11/4193 , G11C7/10 , G11C7/22 , G11C11/406 , G11C11/407 , G11C11/4195 , G11C11/4197 , G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要翻译：提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息，一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。

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