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    • 92. 发明授权
    • Address arithmetic circuit of a memory unit utilized in a processing
system of digitalized analogue signals
    • 在数字化模拟信号的处理系统中使用的存储器单元的地址运算电路
    • US4594687A
    • 1986-06-10
    • US517348
    • 1983-07-26
    • Takao KanekoHironori YamauchiAtsushi Iwata
    • Takao KanekoHironori YamauchiAtsushi Iwata
    • G06F12/02G06F17/14G11C8/04G06F12/00G10L3/02
    • G11C8/04
    • A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc. The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits. The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder. The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder. The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing. According to the type of processing algorithms and corresponding addressing modes, the arithmetic circuit performs the resetting or incrementing of the two counters, controlling the selection operation of the two selection circuits, controlling the number of shifts of the shift circuit, and resetting the third register.
    • 信号地址运算电路用于执行执行自适应预测编码,预测编码中的自适应位分配,自适应变换编码等模拟信号算法所需的地址运算。地址运算电路由两个计数器,三个寄存器,二个 选择器,移位电路,加法器和与门电路。 第一选择器选择第一计数器,第二计数器或第一寄存器中的任一个,并且其输出被加到加法器的一个输入端。 第二选择器选择第二计数器或第三寄存器中的任一个,并且其输出被直接施加到加法器的另一个输入。 加法器的输出和每个位的第二寄存器的内容被加到与门电路,其输出被设置在第三寄存器中,其内容用于存储器寻址。 根据处理算法的类型和相应的寻址模式,算术电路执行两个计数器的复位或递增,控制两个选择电路的选择操作,控制移位电路的移位数,以及复位第三寄存器 。
    • 93. 发明授权
    • Analog to digital converter
    • 模数转换器
    • US4415882A
    • 1983-11-15
    • US299121
    • 1981-09-03
    • Yukio AkazawaYasuyuki MatsuyaAtsushi Iwata
    • Yukio AkazawaYasuyuki MatsuyaAtsushi Iwata
    • H03M1/10H03M1/00H03M1/06H03M1/38H03M1/46H03M1/68H03K13/02
    • H03M1/069H03M1/466H03M1/68
    • The analog output from a local DAC comprising an LDAC and an MDAC, in which the full scale of the LDAC is always larger than the quantized level of the MDAC, is compared with an input analog signal which is sampled and held. A digital code obtained by successive approximation in accordance with the result of the comparison is stored in a successive approximation register. A shift code for calibrating the D/A conversion in the local DAC by shifting the digital code which is previously allotted to each digital code is stored in a shift code generating circuit (ROM). The digital code from the successive approximation register is digitally shifted in accordance with the shift code by a code shift circuit such as a digital adder/subtractor to obtain an A/D conversion output. An analog to digital converter with a high accuracy and an improved conversion speed is inexpensively fabricated in the form of a one chip LSI by a usual CMOS process.
    • 来自包括LDAC和MDAC的本地DAC的模拟输出与其中采样和保持的输入模拟信号进行比较,其中LDAC的满量程总是大于MDAC的量化电平。 通过根据比较结果逐次逼近获得的数字码被存储在逐次逼近寄存器中。 用于通过将预先分配给每个数字代码的数字代码移位来校准本地DAC中的D / A转换的移位代码被存储在移位代码产生电路(ROM)中。 来自逐次逼近寄存器的数字代码通过诸如数字加法器/减法器之类的代码移位电路根据移位代码进行数字移位,以获得A / D转换输出。 具有高精度和高转换速度的模数转换器通过通常的CMOS工艺以单芯片LSI的形式被廉价地制造。