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91. 发明授权

US06404264B2 Fuse latch having multiplexers with reduced sizes and lower power consumption 有权
标题翻译：保险丝锁存器具有减小尺寸和较低功耗的多路复用器
公开(公告)号：US06404264B2
公开(公告)日：2002-06-11
申请号：US09455118
申请日：1999-12-06
申请人： Gabriel Daniel , Toshiaki Kirihata
发明人： Gabriel Daniel , Toshiaki Kirihata
IPC分类号： H03K1762
CPC分类号： G11C29/83 , G11C8/08 , G11C17/18
摘要： A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.
摘要翻译：根据本发明的用于存储器电路的熔丝锁存器包括多个地址线，从熔丝提供的控制信号线，多路复用器，用于响应于控制信号多路复用多个地址线，其中多路复用器仅具有一种类型晶体管和用于从多路复用器接收多路复用信号的解码器。由于多路复用器具有比常规CMOS多路复用器更小的尺寸，因此本发明的熔丝锁存电路具有比常规熔丝锁存器更小的尺寸。多路复用器优选地仅具有NMOS晶体管。为了克服由于NMOS阈值电压引起的电压降，本发明使用低阈值NMOS和/或升压多路复用器中的晶体管。或者，通过使用动态逻辑电路将电压降成功地转换成CMOS电平。此外，通过采用可施加较低电压电平的NMOS晶体管来减少本发明的熔丝锁存电路的电流消耗。

92. 发明授权

US06326800B1 Self-adjusting burn-in test 失效
标题翻译：自调整老化试验
公开(公告)号：US06326800B1
公开(公告)日：2001-12-04
申请号：US09329895
申请日：1999-06-10
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G01R3102
CPC分类号： G01R31/287 , G01R31/2879
摘要： A method and apparatus for providing a self-adjusting burn-in test to a device-under-test by dynamically regulating critical burn-in test parameters, such as the supply voltage, and modifying the test conditions, avoiding in the process over and under burn-in. More specifically, the method includes setting an initial set of burn-in operating test conditions and repeatedly adjusting the burn-in operating test conditions while performing the burn-in test until a predetermined reliability target is achieved. The apparatus being described includes a test target, a tester, a reliability analyzer, and a burn-in controller. With this system, the number of fails are measured during burn-in, and the final number of fails after completion of the burn-in test is extrapolated. If the number of fails exceeds a stated reliability objective, the burn-in conditions specified by burn-in controller are reduced, thereby avoiding over burn-in or in the alternative under-burn.
摘要翻译：一种用于通过动态调节关键老化测试参数（如电源电压）和修改测试条件来为待测器件提供自调整老化测试的方法和设备，避免在过程中和在以下过程老化更具体地，该方法包括设置初始的老化操作测试条件集合并且在执行老化测试期间重复地调整老化操作测试条件，直到达到预定的可靠性目标。所描述的装置包括测试目标，测试器，可靠性分析器和老化控制器。使用该系统，在老化期间测量故障次数，并且推断完成老化测试后的最终失败次数。如果故障次数超过规定的可靠性目标，则老化控制器指定的老化条件减少，从而避免过度烧伤或替代烧伤。

93. 发明授权

US06266272B1 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells 有权
标题翻译：由用作DRAM单元和EPROM单元的多个单晶体管单元形成的部分非易失性动态随机存取存储器
公开(公告)号：US06266272B1
公开(公告)日：2001-07-24
申请号：US09364841
申请日：1999-07-30
申请人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
发明人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
IPC分类号： G11C1450
CPC分类号： G11C16/02 , G11C11/005
摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.
摘要翻译：部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。电池可电可编程为非易失性存储器。这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

94. 发明授权

US6081021A Conductor-insulator-conductor structure 失效
标题翻译：导体 - 绝缘体导体结构
公开(公告)号：US6081021A
公开(公告)日：2000-06-27
申请号：US7889
申请日：1998-01-15
申请人： Jeffrey P. Gambino , Chandrasekhar Narayan , Toshiaki Kirihata
发明人： Jeffrey P. Gambino , Chandrasekhar Narayan , Toshiaki Kirihata
IPC分类号： H01L21/02 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/00
CPC分类号： H01L28/40 , H01L21/76807 , H01L21/76831 , H01L21/76838 , H01L21/76885 , H01L23/5252 , H01L28/60 , H01L21/31612 , H01L21/3185 , H01L2924/0002
摘要： An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.
摘要翻译：一种包括导体 - 绝缘体 - 导体结构的集成电路器件以及同时形成双重镶嵌通孔同时制造该结构的方法。第一互连层形成在第一层间电介质上。开口延伸穿过第二层间介质到第一互连层。绝缘体沉积在开口中。然后将沟槽蚀刻到将成为通孔的开口的上部中，同时从将成为通孔的开口的底部移除绝缘体。然后将导体沉积在开口中并在沟槽中，并使用化学机械抛光（CMP）来对导体进行图案化。然后沉积第三层间电介质，形成延伸到导体的开口，并且沉积和图案化第三互连层导体。

95. 发明授权

US5940335A Prioritizing the repair of faults in a semiconductor memory device 失效
标题翻译：对半导体存储器件中的故障进行优先排序
公开(公告)号：US5940335A
公开(公告)日：1999-08-17
申请号：US122426
申请日：1998-07-24
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808
摘要： A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
摘要翻译：用于使存储器容错的可变大小冗余替换（VSRR）布置。支持存储器的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。用于修复存储器故障的冗余单元是独立控制的。维修单元内的所有冗余元件优选同时更换。冗余单元中的冗余元件通过解码地址线来控制。表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。这种配置可显着降低由添加的冗余元件和控制电路产生的开销，同时提高访问速度并降低功耗。最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

96. 发明授权

US5764655A Built in self test with memory 失效
标题翻译：内置自检
公开(公告)号：US5764655A
公开(公告)日：1998-06-09
申请号：US887374
申请日：1997-07-02
申请人： Toshiaki Kirihata , Christopher D. Wait
发明人： Toshiaki Kirihata , Christopher D. Wait
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/273 , G11C29/12 , H01L21/66 , G06F11/00
CPC分类号： G06F11/2635 , G01R31/318505 , G01R31/31702
摘要： An integrated circuit chip and an electronic system are disclosed, each incorporating a self-test system. The integrated circuit chip includes capability for Built In Self Test (BIST) and a non-volatile memory where the BIST may be self-programmable. The electronic system comprises, an integrated circuit chip which includes on the chip Built In Self Test (BIST) and a non-volatile memory, together with an off-chip test target. The integrated circuit chip and the electronic system are particularly useful for simplifying the testing of electronic products both in manufacturing and in the field, and are even more particularly useful in eliminating the need for large, complex, high speed testers in the manufacturing environment, substituting instead a simple power chuck to plug the product into.
摘要翻译：公开了一种集成电路芯片和电子系统，其中包括自检系统。集成电路芯片包括内置自检（BIST）和非易失性存储器，其中BIST可以是自编程的。电子系统包括集成电路芯片，其包括芯片内置自测（BIST）和非易失性存储器，以及片外测试目标。集成电路芯片和电子系统对于简化制造和现场的电子产品的测试特别有用，并且甚至更具体地用于消除在制造环境中对大型，复杂的高速测试仪的需要，代替而是一个简单的动力卡盘来插入产品。

97. 发明授权

US5257232A Sensing circuit for semiconductor memory with limited bitline voltage swing 失效
标题翻译：具有有限位线电压摆幅的半导体存储器的感应电路
公开(公告)号：US5257232A
公开(公告)日：1993-10-26
申请号：US847769
申请日：1992-03-05
申请人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
发明人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
IPC分类号： G11C11/409 , G11C7/06 , G11C11/407 , G11C11/4091 , G11C13/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

98. 发明授权

US07817455B2 Random access electrically programmable e-fuse ROM 有权
标题翻译：随机存取电可编程电子熔丝ROM
公开(公告)号：US07817455B2
公开(公告)日：2010-10-19
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

99. 发明申请

US20080316789A1 Random Access Electrically Programmable E-Fuse Rom 有权
标题翻译：随机存取电子可编程电子保险丝
公开(公告)号：US20080316789A1
公开(公告)日：2008-12-25
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00 , G11C17/16
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。字线选择通过在VDD处工作的解码逻辑进行，而位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

100. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

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