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91. 发明申请

US20120039247A1 FRONT-END FOR SATELLITE COMMUNICATION 有权
标题翻译：前端用于卫星通信
公开(公告)号：US20120039247A1
公开(公告)日：2012-02-16
申请号：US13257981
申请日：2010-04-25
申请人： Daniel Wajcer , Guy Cohen
发明人： Daniel Wajcer , Guy Cohen
IPC分类号： H04W88/04 , H04W74/00 , H04B7/00
CPC分类号： H04B7/18582 , H04B7/18508 , H04B7/18513 , H04B7/18584 , H04L1/005 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0071 , H04L1/0072 , H04W84/06 , H04W88/06
摘要： A communication method includes operating a communication unit (60, 124), which demodulates radio signals in accordance with a first air interface and applies at least one upper-layer process to the demodulated signals. A signal is received and demodulated in accordance with a second air interface, different from the first air interface. The demodulated signal is input to the communication unit so as to cause the communication unit to apply the upper-layer process to the signal that was demodulated using the second air interface, while superseding the first air interface.
摘要翻译：通信方法包括操作通信单元（60,124），该通信单元根据第一空中接口对无线电信号进行解调，并对解调的信号应用至少一个上层处理。根据与第一空中接口不同的第二空中接口接收和解调信号。解调后的信号被输入到通信单元，以使得通信单元在取代第一空中接口的同时使上层处理应用于使用第二空中接口解调的信号。

92. 发明申请

US20120029856A1 METHOD AND SYSTEM FOR PROVIDING PROCESS TOOL CORRECTABLES 有权
标题翻译：提供过程工具修正的方法和系统
公开(公告)号：US20120029856A1
公开(公告)日：2012-02-02
申请号：US13185033
申请日：2011-07-18
申请人： Guy Cohen , Dana Klein , Pavel Izikson
发明人： Guy Cohen , Dana Klein , Pavel Izikson
IPC分类号： G06F19/00
CPC分类号： G05B19/41875 , G05B2219/32182 , Y02P90/22
摘要： The present invention may include performing a first measurement process on a wafer of a lot of wafers, wherein the first measurement process includes measuring one or more characteristics of a plurality of targets distributed across one or more fields of the wafer, determining a set of process tool correctables for a residual larger than a selected threshold level utilizing a loss function, wherein the loss function is configured to fit a model for one or more process tools, as a function of field position, to one or more of the measured characteristics of the plurality of targets, wherein the set of process tool correctables includes one or more parameters of the model that act to minimize the difference between a norm of the residual and the selected threshold, and utilizing the determined process tool correctables to monitor or adjust one or more processes of the process tools.
摘要翻译：本发明可以包括对许多晶片的晶片执行第一测量过程，其中第一测量过程包括测量分布在晶片的一个或多个场上的多个目标的一个或多个特性，确定一组过程用于利用损失函数对大于所选阈值的残差的工具进行校正，其中所述损失函数被配置为将作为场位置的函数的一个或多个处理工具的模型拟合到一个或多个所测量的特征多个目标，其中所述一组处理工具可校正包括模型的一个或多个参数，其用于最小化残差范数与所选择的阈值之间的差异，并且利用所确定的处理工具可校正来监视或调整一个或多个流程工具的流程。

93. 发明申请

US20110249489A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20110249489A1
公开(公告)日：2011-10-13
申请号：US12758939
申请日：2010-04-13
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： G11C11/00 , H01L21/8238 , H01L21/336 , H03K19/20
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
摘要翻译：逆变器装置包括连接到电压源节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一p型场效应晶体管（pFET）器件和第一n型场效应晶体管（nFET ）器件，其具有设置在第一纳米线上的栅极。

94. 发明申请

US20110233522A1 p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors 有权
标题翻译：具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET
公开(公告)号：US20110233522A1
公开(公告)日：2011-09-29
申请号：US12731241
申请日：2010-03-25
申请人： Guy Cohen , Conal E. Murray , Michael J. Rooks
发明人： Guy Cohen , Conal E. Murray , Michael J. Rooks
IPC分类号： H01L29/267 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/42392 , H01L29/7848 , H01L29/785
摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
摘要翻译：提供了在纳米级基于沟道的场效应晶体管（FET）中嵌入硅锗（e-SiGe）源极和漏极应力的技术。一方面，制造FET的方法包括以下步骤。提供其上具有电介质的掺杂衬底。在电介质上放置至少一个硅（Si）纳米线。掩模纳米线的一个或多个部分，使纳米线的其它部分暴露出来。外延锗（Ge）生长在纳米线的暴露部分上。外延Ge与纳米线中的Si相互扩散以形成纳米线中嵌入纳米线中的压应变的SiGe区域。掺杂衬底用作FET的栅极，纳米线的掩蔽掉的部分用作FET的沟道，并且嵌入的SiGe区域用作FET的源极和漏极区域。

95. 发明申请

US20110109952A1 NONVOLATILE NANO-ELECTROMECHANICAL SYSTEM DEVICE 有权
标题翻译：非挥发性纳米机电系统装置
公开(公告)号：US20110109952A1
公开(公告)日：2011-05-12
申请号：US12615358
申请日：2009-11-10
申请人： David J. Frank , Guy Cohen
发明人： David J. Frank , Guy Cohen
IPC分类号： G02B26/08 , H02N10/00 , H01S4/00
CPC分类号： B81B3/0072 , B81B2201/018 , B81B2203/0118 , B81B2207/053 , B81C2201/0167
摘要： A nonvolatile nano-electromechanical system device is provided and includes a cantilever structure, including a beam having an initial shape, which is supported at one end thereof by a supporting base and a beam deflector, including a phase change material (PCM), disposed on a portion of the beam in a non-slip condition with a material of the beam, the PCM taking one of an amorphous phase or a crystalline phase and deflecting the beam from the initial shape when taking the crystalline phase.
摘要翻译：提供了非易失性纳米机电系统装置，其包括悬臂结构，其包括具有初始形状的梁，所述梁的一端由支撑基座支撑，并且梁偏转器包括相变材料（PCM），所述相变材料光束的一部分处于防滑状态，具有光束的材料，PCM采取非晶相或结晶相中的一种，并且在获取结晶相时将光束从初始形状偏转。

96. 发明授权

US07884004B2 Maskless process for suspending and thinning nanowires 有权
标题翻译：用于悬浮和稀化纳米线的无掩模工艺
公开(公告)号：US07884004B2
公开(公告)日：2011-02-08
申请号：US12365623
申请日：2009-02-04
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

97. 发明申请

US20100052018A1 CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS 有权
标题翻译：连续金属半导体合金通过互连
公开(公告)号：US20100052018A1
公开(公告)日：2010-03-04
申请号：US12198592
申请日：2008-08-26
申请人： Guy Cohen , Christos D. Dimitrakopoulos , Alfred Grill
发明人： Guy Cohen , Christos D. Dimitrakopoulos , Alfred Grill
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/28518 , H01L21/76885 , H01L23/481 , H01L29/665 , H01L29/78 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy can be derived from either a semiconductor nanowire or an epitaxial grown semiconductor material. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. The lower portion of the continuous metal semiconductor alloy and the vertical pillar portion are not separated by a material interface. Instead, the two portions of the continuous metal semiconductor alloy are of unitary construction, i.e., a single piece.
摘要翻译：公开了一种接触结构，其中连续的金属半导体合金位于包含在电介质材料内的通孔内。连续半导体金属合金与位于连续半导体金属合金顶部的第一金属水平的上金属线和至少位于连续金属半导体合金下方的源极和漏极扩散区的表面直接接触。连续金属半导体合金可以衍生自半导体纳米线或外延生长半导体材料。连续金属半导体合金包括包含在每个源极和漏极区域的上表面内的下部以及从下部向上延伸的垂直柱部分。连续金属半导体合金的下部和垂直支柱部分不被材料界面分离。相反，连续金属半导体合金的两个部分是单一结构，即单件。

98. 发明授权

US07659200B2 Self-constrained anisotropic germanium nanostructure from electroplating 失效
标题翻译：电镀自限制各向异性锗纳米结构
公开(公告)号：US07659200B2
公开(公告)日：2010-02-09
申请号：US11620391
申请日：2007-01-05
申请人： Guy Cohen , Qiang Huang , Lubomyr T. Romankiw , Hariklia Deligianni
发明人： Guy Cohen , Qiang Huang , Lubomyr T. Romankiw , Hariklia Deligianni
IPC分类号： H01L21/302
CPC分类号： C25D3/54 , B82Y10/00 , C25D5/022 , C25D7/123 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/02628 , H01L21/02639 , Y10S977/762
摘要： A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.
摘要翻译：提供包括锗的纳米结构，其包括直径小于1微米的导线和宽度小于1微米的与基底接触并从基底向外延伸的纳米结构以及制备方法。

99. 发明申请

US20090003073A1 Rd Algorithm Improvement for Nrom Technology 有权
标题翻译： Nrom技术的Rd算法改进
公开(公告)号：US20090003073A1
公开(公告)日：2009-01-01
申请号：US12087594
申请日：2007-01-10
申请人： Arik Rizel , Guy Cohen
发明人： Arik Rizel , Guy Cohen
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0475 , G11C16/26
摘要： Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.
摘要翻译：通过使用读取电压的初始值并执行读取操作来选择NVM单元的读取电压电平，将发现的实际位数与预期位数进行比较，如果实际数字与基于可用数据，如可用统计数据，级别占用，邻居级别，先前块数据以及在读取，编程或擦除期间使用的其他数据的可变数据来调整读取电压电平。例如，基于多个丢失比特，或者基于先前读取操作的结果，或者在另一程序级别获得的结果，或者存储器单元已循环多少次，或者存储器单元处于多少每个节目级别，或者在所选择的存储器块中的另一程序级别的多个位上。

100. 发明授权

US07457183B2 Operating array cells with matched reference cells 有权
标题翻译：具有匹配参考单元的操作阵列单元
公开(公告)号：US07457183B2
公开(公告)日：2008-11-25
申请号：US11580995
申请日：2006-10-16
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

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