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91. 发明申请

US20120281464A1 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate 有权
标题翻译：使用字线过驱动和高k金属栅极提高磁隧道接头的编程电流
公开(公告)号：US20120281464A1
公开(公告)日：2012-11-08
申请号：US13550262
申请日：2012-07-16
申请人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
发明人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1657 , G11C11/1659
摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
摘要翻译：操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）装置的MRAM单元; 以及选择器，包括串联耦合到MTJ器件的源极 - 漏极路径。该方法还包括将过驱动电压施加到选择器的门以接通选择器。

92. 发明授权

US08223575B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08223575B2
公开(公告)日：2012-07-17
申请号：US11715631
申请日：2007-03-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置为产生两个或多个电压电平的可变电源。

93. 发明申请

US20120127788A1 MRAM Cells and Circuit for Programming the Same 有权
标题翻译： MRAM单元及其编程电路
公开(公告)号：US20120127788A1
公开(公告)日：2012-05-24
申请号：US13364955
申请日：2012-02-02
申请人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
发明人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1677 , G11C11/1675
摘要： A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.
摘要翻译：电路包括磁阻随机存取存储器（MRAM）单元和控制电路。控制电路电耦合到MRAM单元，并且包括被配置为提供第一写入脉冲以将值写入MRAM单元的电流源和被配置为测量MRAM单元的状态的读取电路。控制电路还被配置为验证通过第一写入脉冲是否实现了成功写入。

94. 发明申请

US20100254181A1 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate 有权
标题翻译：使用字线过驱动和高k金属栅极提高磁隧道接头的编程电流
公开(公告)号：US20100254181A1
公开(公告)日：2010-10-07
申请号：US12687747
申请日：2010-01-14
申请人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
发明人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
IPC分类号： G11C11/00 , G11C11/14 , G11C5/14
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1657 , G11C11/1659
摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
摘要翻译：操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）装置的MRAM单元; 以及选择器，包括串联耦合到MTJ器件的源极 - 漏极路径。该方法还包括将过驱动电压施加到选择器的门以接通选择器。

95. 发明申请

US20090251975A1 Circuit and Method for a Sense Amplifier with Instantaneous Pull Up/Pull Down Sensing 有权
标题翻译：一种具有瞬时上拉/下拉传感的读出放大器的电路和方法
公开(公告)号：US20090251975A1
公开(公告)日：2009-10-08
申请号：US12062320
申请日：2008-04-03
申请人： Shine Chung , Jonathan Hung
发明人： Shine Chung , Jonathan Hung
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/062
摘要： A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches.
摘要翻译：一种用于感测放大器的电路和方法，用于感测当选择信号将存储器单元耦合到感测放大器时所存储的电荷。立即将上拉电压和下拉电压提供给读出放大器以感测互补位线上的小信号差分输入，并同时恢复存储在存储单元中的值。提供差分输出信号发生器电路以瞬时提供上拉和下拉电压。在另一优选实施例中，信号发生器在第一电平上提供上拉和下拉电压，随后将上拉电压增加到大于正电源电压的电压并降低下拉电压。公开了一种感测方法，其中感测和恢复动作被立即执行以提供具有更大的设备不匹配容限的存储器单元感测。

96. 发明授权

US07592649B2 Memory word lines with interlaced metal layers 有权
标题翻译：记忆字线与交错金属层
公开(公告)号：US07592649B2
公开(公告)日：2009-09-22
申请号：US12100866
申请日：2008-04-10
申请人： Shine Chung , Cheng-Hsien Hung
发明人： Shine Chung , Cheng-Hsien Hung
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , H01L27/10894
摘要： A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.
摘要翻译：公开了一种具有改进的字线结构的存储器件。存储器件包括在衬底上基本上彼此平行的多个多晶硅条，多个多晶硅条布置在第一组和第二组的两个交替组中。存储器件还包括形成多个位线的第一层导电条和第二层餐条，第二层导电条覆盖在多晶硅条上并耦合到第一组多晶硅条。此外，存储器件包括形成一个或多个电源线的第三层导电条和第四层金属条，第四层导电条覆盖在第二层导电条上，并连接到第二组多晶硅条以形成具有低电阻的新字线结构。

97. 发明授权

US07432578B1 CMOS image sensor with enhanced photosensitivity 有权
标题翻译：具有增强光敏性的CMOS图像传感器
公开(公告)号：US07432578B1
公开(公告)日：2008-10-07
申请号：US11739650
申请日：2007-04-24
申请人： Shine Chung , Shou-Gwo Wuu
发明人： Shine Chung , Shou-Gwo Wuu
IPC分类号： H01L31/06 , H01L31/0232
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/14645 , H01L27/14663 , H01L27/14696
摘要： A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially covering the reverse biased device, the photosensitive layer releasing electrons and holes when struck by photons, wherein the photon generated electrons and holes in the photosensitive layer reach the reverse biased device and create a combination current therein when a light shines thereon.
摘要翻译：公开了一种光敏器件，其包括半导体衬底，形成在半导体衬底中的至少一个反向偏压器件，例如PN结二极管，以及设置在半导体衬底之上并基本上覆盖反向偏置器件的至少一个感光层，光敏层在被光子撞击时释放电子和空穴，其中光子产生的电子和感光层中的空穴到达反向偏置器件，并且当光照射在其上时产生组合电流。

98. 发明申请

US20080062795A1 Method and system for DRAM sensing 有权
公开(公告)号：US20080062795A1
公开(公告)日：2008-03-13
申请号：US11517674
申请日：2006-09-08
申请人： Shine Chung
发明人： Shine Chung
IPC分类号： G11C11/24 , G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C2207/2227
摘要： This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

99. 发明申请

US20070279816A1 SYSTEM TO PROTECT ELECTRICAL FUSES 有权
标题翻译：保护电熔丝的系统
公开(公告)号：US20070279816A1
公开(公告)日：2007-12-06
申请号：US11839966
申请日：2007-08-16
申请人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
发明人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
IPC分类号： H02H9/04 , H03K19/003
CPC分类号： G11C17/16 , G11C17/18
摘要： A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.
摘要翻译：公开了一种用于保护电熔丝电路的方法和系统。具有静电放电（ESD）保护的电熔丝电路具有至少一个电熔丝，与至少一晶体管串联耦合的编程装置，用于接收用于控制流经电熔丝的编程电流的控制信号，电压源耦合到熔丝和用于提供编程电流的编程装置，以及保护模块，其在其第一端耦合到晶体管的栅极，以减少由于到达电压的电静电而在晶体管的栅极处累积的电荷源，从而防止编程设备意外编程保险丝。

100. 发明申请

US20060238220A1 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US20060238220A1
公开(公告)日：2006-10-26
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
发明人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
IPC分类号： H03K19/0175
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

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