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91. 发明申请

US20060136858A1 Utilizing fuses to store control parameters for external system components 审中-公开
标题翻译：利用保险丝存储外部系统组件的控制参数
公开(公告)号：US20060136858A1
公开(公告)日：2006-06-22
申请号：US11016214
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G11C17/18
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

92. 发明申请

US20060131743A1 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20060131743A1
公开(公告)日：2006-06-22
申请号：US11016220
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H01L23/48
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

93. 发明申请

US20050212087A1 STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED COLLECTOR-BASED CAPACITANCE 失效
标题翻译：具有减少集电极电容的双极晶体管的结构和方法
公开(公告)号：US20050212087A1
公开(公告)日：2005-09-29
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/102 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

94. 发明授权

US06940149B1 Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base 失效
标题翻译：形成在发射极和非本征基底之间具有空隙的双极晶体管的结构和方法
公开(公告)号：US06940149B1
公开(公告)日：2005-09-06
申请号：US10708563
申请日：2004-03-11
申请人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
发明人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/737 , H01L31/072
CPC分类号： H01L29/66242 , H01L27/0623 , H01L29/0649 , H01L29/7378
摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
摘要翻译：提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括一个气隙和一个真空空隙。

95. 发明申请

US20050167786A1 STRUCTURE AND METHOD FOR LOCAL RESISTOR ELEMENT IN INTEGRATED CIRCUIT TECHNOLOGY 有权
标题翻译：集成电路技术中的局部电阻元件的结构与方法
公开(公告)号：US20050167786A1
公开(公告)日：2005-08-04
申请号：US10708023
申请日：2004-02-03
申请人： Jason Gill , Terence Hook , Randy Mann , William Murphy , William Tonti , Steven Voldman
发明人： Jason Gill , Terence Hook , Randy Mann , William Murphy , William Tonti , Steven Voldman
IPC分类号： H01L21/8244 , H01L27/02 , H01L27/08 , H01L27/11 , H01L27/12 , H01L27/082
CPC分类号： H01L27/11 , H01L27/0288 , H01L27/0802 , H01L27/1112 , H01L27/1203 , H01L29/7304 , H01L29/7378 , H01L29/7391 , H01L29/78 , Y10S257/903 , Y10S257/904
摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.
摘要翻译：一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

96. 发明授权

US06882027B2 Methods and apparatus for providing an antifuse function 有权
标题翻译：提供反熔丝功能的方法和装置
公开(公告)号：US06882027B2
公开(公告)日：2005-04-19
申请号：US10447018
申请日：2003-05-28
申请人： Axel Brintzinger , Carl Radens , William Tonti
发明人： Axel Brintzinger , Carl Radens , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.
摘要翻译：公开了用于提供反熔丝的方法和装置，其中反熔丝包括具有由浅沟槽隔离（STI）边界限定的有源区的半导体衬底; 栅极导体，其设置在所述半导体衬底上方并且覆盖所述STI边界的至少一部分; 设置在所述半导体衬底和所述栅极导体之间的电介质; 耦合到所述栅极导体的第一端子; 以及耦合到所述半导体衬底的第二端子，其中所述电介质的击穿导致所述栅极导体的区域和所述有源区域的区域之间的电连接包括基本上靠近所述STI边界。

97. 发明申请

US20050073354A1 VOLTAGE DIVIDER FOR INTEGRATED CIRCUITS 失效
标题翻译：用于集成电路的电压分压器
公开(公告)号：US20050073354A1
公开(公告)日：2005-04-07
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi Abadeer , John Fifield , William Tonti
发明人： Wagdi Abadeer , John Fifield , William Tonti
IPC分类号： G11C5/14 , H01L27/08 , H01L27/088 , H02J1/00 , H02M3/00
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

98. 发明申请

US20130001789A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20130001789A1
公开(公告)日：2013-01-03
申请号：US13617060
申请日：2012-09-14
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

99. 发明授权

US08288276B2 Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion 有权
标题翻译：形成包括位于底部通孔部分的金属界面层的互连结构的方法
公开(公告)号：US08288276B2
公开(公告)日：2012-10-16
申请号：US12346040
申请日：2008-12-30
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

100. 发明授权

US08232177B2 Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure 有权
标题翻译：在衬底中产生均匀排列的阱和隔离区域以及所得结构的方法
公开(公告)号：US08232177B2
公开(公告)日：2012-07-31
申请号：US12570415
申请日：2009-09-30
申请人： Wagdi Abadeer , Lilian Kamal, legal representative , Kiran V Chatty , Robert J Gauthier, Jr. , Jed H Rankin , Robert R Robison , William Tonti
发明人： Wagdi Abadeer , Kiran V Chatty , Robert J Gauthier, Jr. , Jed H Rankin , Robert R Robison , William Tonti
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

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