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91. 发明授权

US06154874A Memory-saving method and apparatus for partitioning high fanout nets 失效
标题翻译：用于分割高扇出网络的存储器保存方法和装置
公开(公告)号：US06154874A
公开(公告)日：2000-11-28
申请号：US62219
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements. Said elementary pairs are identified by determining for each pin in said net a relative x-coordinate and a relative y-coordinate, constructing for each pin a combined binary coordinate as a function of the pin's relative x-coordinate and relative y-coordinate, ordering the pins in accordance with their respective combined binary coordinates, iteratively combining the pins until one pin remains, and iteratively expanding the pins.
摘要翻译：本发明的目的是提供一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。通过确定所述网中的每个针的相对x坐标和相对的y坐标来识别所述基本对，所述相对的x坐标和相对的y坐标构成了作为销的相对x坐标和相对y坐标的函数的组合二进制坐标根据它们各自组合的二进制坐标的引脚，迭代地组合引脚直到保持一个引脚，并且迭代地扩展引脚。

92. 发明授权

US08806227B2 Data shredding RAID mode 有权
标题翻译：数据粉碎RAID模式
公开(公告)号：US08806227B2
公开(公告)日：2014-08-12
申请号：US11620794
申请日：2007-01-08
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Ranko Scepanovic , Robert D. Waldron
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Ranko Scepanovic , Robert D. Waldron
IPC分类号： G06F12/14 , G06F21/62
CPC分类号： G06F21/6218
摘要： A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.
摘要翻译：一种通过产生随机化值来存储敏感数据的方法，将敏感数据和随机化值变换为结果，并将结果的分离部分存储在至少两个存储设备上，使得如果敏感数据中的任何一个存储设备受到损害。

93. 发明申请

US20120278775A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20120278775A1
公开(公告)日：2012-11-01
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

94. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

95. 发明授权

US07739575B2 Pipelined LDPC arithmetic unit 失效
标题翻译：流水线LDPC运算单元
公开(公告)号：US07739575B2
公开(公告)日：2010-06-15
申请号：US11626400
申请日：2007-01-24
申请人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
发明人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/1145
摘要： An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1 representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.
摘要翻译：对低密度奇偶校验解码器的算术单元的改进，其中算术单元具有模块的流水线架构。第一模块计算md_R和md_g_in的绝对值之间的差值，并将结果传递给第一个Gallager模块。第一个Gallager模块将该值从p0 / p1表示转换为2 * p0-1表示，并将结果传递给第二个模块。第二个模块根据md_g_in和md_R的符号值有选择地调整前一个模块的结果，并将其一个输出传递给第三个模块（另外两个输出loc_item_out和hard_out不是流水线的一部分）。第三个模块通过添加第二个模块的结果和loc_item_in来计算一个新的md_g值，并将该结果传递给第四个模块。第四个模块分离新的md_g的符号和绝对值，并将结果传递给第二个Gallager模块。第二个Gallager模块将2 * p0-1表示的结果转换为p0 / p1表示，最终值将单位设为md_g_out。在这些计算中，md_R =来自前一次迭代的校验节点值，md_g =边缘值（md_g_in - 来自上一次迭代，md_g_out-用于下一次迭代），p0 =值为零的概率，p1 = 值为1，loc_item_in / loc_item_out =用于md_g_out计算的中间值，hard_out =流水线运算单元当前迭代的位值估计。

96. 发明申请

US20090309770A1 METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES 有权
标题翻译：用于可编程解码大量代码类型的方法和装置
公开(公告)号：US20090309770A1
公开(公告)日：2009-12-17
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译：提供了用于多种代码类型的可编程解码的方法和装置。提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。通过将数据写入到通信网络的目标地址来交织数据。通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。

97. 发明授权

US07584442B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

98. 发明申请

US20090133003A1 COMMAND LANGUAGE FOR MEMORY TESTING 有权
标题翻译：用于记忆测试的命令语言
公开(公告)号：US20090133003A1
公开(公告)日：2009-05-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

99. 发明申请

US20080049719A1 MEMORY MAPPING FOR PARALLEL TURBO DECODING 失效
标题翻译：用于并行涡轮解码的记忆映射
公开(公告)号：US20080049719A1
公开(公告)日：2008-02-28
申请号：US11924385
申请日：2007-10-25
申请人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
发明人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
IPC分类号： H04L13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入端的位的值，以直接或转置的顺序向两个输出提供两个输入端的信号。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

100. 发明申请

US20070113212A1 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

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