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91. 发明授权

US6063664A Method of making EEPROM with trenched structure 失效
标题翻译：制造具有沟槽结构的EEPROM的方法
公开(公告)号：US6063664A
公开(公告)日：2000-05-16
申请号：US49215
申请日：1998-03-27
申请人： Jong Chen , Chrong Jung Lin , Di-Son Kuo
发明人： Jong Chen , Chrong Jung Lin , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/42336
摘要： A new method of forming a trenched floating gate in the fabrication of a EEPROM memory cell is described. A trench is etched into a semiconductor substrate. Ions are implanted into the surface of the semiconductor substrate and into the semiconductor substrate surrounding the trench to form N+ regions. A gate oxide layer is grown over the surface of the semiconductor substrate and within the trench. The gate oxide within a tunneling window overlying one of the N+ regions is removed and a tunnel oxide is grown in the tunneling window. A polysilicon layer is deposited over the surface of the semiconductor substrate and within the trench and patterned to form a floating gate within the trench and on the surface of the substrate wherein the floating gate contacts the N+ region through the tunneling window.
摘要翻译：描述了在EEPROM存储器单元的制造中形成沟槽浮动栅极的新方法。将沟槽蚀刻到半导体衬底中。将离子注入到半导体衬底的表面中并进入围绕沟槽的半导体衬底中以形成N +区。在半导体衬底的表面上并在沟槽内生长栅极氧化物层。覆盖N +区域之一的隧道窗内的栅极氧化物被去除并且在隧道窗中生长隧道氧化物。多晶硅层沉积在半导体衬底的表面上并且在沟槽内并且被图案化以在沟槽内和衬底的表面上形成浮置栅极，其中浮动栅极通过隧道窗口接触N +区域。

92. 发明申请

US20050045939A1 Split-gate memory cell, memory array incorporating same, and method of manufacture thereof 审中-公开
标题翻译：分离栅存储器单元，并入其的存储器阵列及其制造方法
公开(公告)号：US20050045939A1
公开(公告)日：2005-03-03
申请号：US10649203
申请日：2003-08-27
申请人： Eungjoon Park , Di-Son Kuo
发明人： Eungjoon Park , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115
摘要： Flash memory cells have a split-gate structure in which the channel region underlies a floating gate of minimum lithography dimension, as well as one or more portions of the control gate that extend along one or more sidewalls of the floating gate. The length of the channel underlying the control gate sidewall portions is independent of the thickness of the floating gate sidewall portions and is smaller than and independent of the minimum lithography dimension. Preferably, the control gate is part of a continuous word line extending over a row of many substantially identical memory cells. Channel length need be no longer that the minimum lithography dimension (the channel portion underlying the floating gate) plus a sufficient additional length to account for the thickness of the inter-poly dielectric on the control gate sidewall or sidewalls, and for sufficient direct control of the channel by the control gate.
摘要翻译：闪存单元具有分裂栅极结构，其中沟道区域位于最小光刻尺寸的浮动栅极之下，以及沿着浮动栅极的一个或多个侧壁延伸的控制栅极的一个或多个部分。控制栅极侧壁部分下方的通道的长度与浮动栅极侧壁部分的厚度无关，并且小于和不依赖于最小光刻尺寸。优选地，控制栅极是连续字线的一部分，该连续字线在许多基本相同的存储单元的行上延伸。通道长度不再需要最小光刻尺寸（浮动栅极下面的沟道部分）加上足够的附加长度来解释控制栅极侧壁或侧壁上的多晶硅电介质的厚度，并且为了足够的直接控制通道由控制门。

93. 发明授权

US6133096A Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices 失效
标题翻译：用于同时制造堆叠栅极闪存单元和浸液式周边器件的工艺
公开(公告)号：US6133096A
公开(公告)日：2000-10-17
申请号：US208917
申请日：1998-12-10
申请人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
发明人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534
摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.
摘要翻译：已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。

94. 发明授权

US6087222A Method of manufacture of vertical split gate flash memory device 失效
公开(公告)号：US6087222A
公开(公告)日：2000-07-11
申请号：US35058
申请日：1998-03-05
申请人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/8247 , H01L21/336
CPC分类号： H01L27/11556 , H01L21/28273
摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

95. 发明授权

US6074915A Method of making embedded flash memory with salicide and sac structure 有权
标题翻译：制造具有自杀和囊结构的嵌入式闪存的方法
公开(公告)号：US6074915A
公开(公告)日：2000-06-13
申请号：US135044
申请日：1998-08-17
申请人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
发明人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.
摘要翻译：公开了一种制造具有自对准接触（SAC）结构的嵌入式闪存单元的组合方法。半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。因此，存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。此外，两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分，而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题，同时去除栅极氧化物在衬底的另一区域中的部分。

96. 发明授权

US6028324A Test structures for monitoring gate oxide defect densities and the plasma antenna effect 失效
标题翻译：用于监测栅极氧化物缺陷密度和等离子体天线效应的测试结构
公开(公告)号：US6028324A
公开(公告)日：2000-02-22
申请号：US813758
申请日：1997-03-07
申请人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
发明人： Hung-Der Su , Jian-Hsing Lee , Di-Son Kuo
IPC分类号： H01L23/544 , H01L23/58 , H01L27/108
CPC分类号： H01L22/34 , H01L2924/0002
摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.
摘要翻译：描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

97. 发明授权

US06495880B2 Method to fabricate a flash memory cell with a planar stacked gate 有权
标题翻译：用平面堆叠栅极制造闪存单元的方法
公开(公告)号：US06495880B2
公开(公告)日：2002-12-17
申请号：US09760309
申请日：2001-01-16
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L29/66825
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的堆叠栅极拓扑的堆叠栅极闪存EEPROM器件的新方法。在半导体衬底上形成隔离区。隧道氧化物层设置在半导体衬底的表面上。沉积在隧道氧化物层上的第一多晶硅层。将第一多晶硅层抛光直到多晶硅的顶表面平坦并平行于半导体衬底的顶表面。蚀刻掉第一多晶硅层以形成浮栅。源极和漏极区域形成在半导体衬底内。沉积在第一多晶硅层上的多层介电层。第二多晶硅层沉积在叠层电介质层上。蚀刻掉第二多晶硅层和互聚电介质层以形成覆盖浮栅的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层的控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

98. 发明授权

US06437397B1 Flash memory cell with vertically oriented channel 有权
标题翻译：具有垂直定向通道的闪存单元
公开(公告)号：US06437397B1
公开(公告)日：2002-08-20
申请号：US09377539
申请日：1999-08-19
申请人： Chrong Jung Lin , Shui-Hung Chen , Jong Chen , Di-Son Kuo
发明人： Chrong Jung Lin , Shui-Hung Chen , Jong Chen , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115
摘要： A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.
摘要翻译：通过以下步骤形成硅半导体衬底上的垂直存储器件。在硅半导体衬底的表面上形成隔离氧化硅结构的阵列。在硅半导体衬底中在阵列中的氧化硅结构之间形成浮栅沟槽，沟槽具有沟槽侧壁表面。通过沟槽侧壁表面用阈值注入来掺杂浮栅沟槽的侧壁。在沟槽侧壁表面上形成隧道氧化物层，隧道氧化物层具有外表面。在隧道氧化物层的外表面上的沟槽中形成浮栅电极。衬底中的源极/漏极区域与浮栅电极自对准。在浮栅电极的顶表面上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极。通过执行自对准蚀刻，然后进行源极线植入的步骤形成源极线。

99. 发明授权

US06391719B1 Method of manufacture of vertical split gate flash memory device 有权
标题翻译：垂直分闸门闪存器件的制造方法
公开(公告)号：US06391719B1
公开(公告)日：2002-05-21
申请号：US09575963
申请日：2000-05-23
申请人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21336
CPC分类号： H01L27/11556 , H01L21/28273
摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
摘要翻译：形成垂直晶体管存储器件的方法包括以下步骤。在形成沟槽之前，在行之间形成FOX区域。在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。在包括沟槽的衬底上形成隧道氧化物层。在隧道氧化物层上形成填充沟槽并在沟槽上方延伸的掺杂多晶硅的覆盖厚的浮栅层。将浮动栅层蚀刻到沟槽顶部的下方。在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。在电极间电介质层上形成掺杂多晶硅的厚度厚的控制栅极层。将控制栅层图案化为控制栅电极。形成与控制栅电极的侧壁相邻的间隔物。

100. 发明授权

US06281545B1 Multi-level, split-gate, flash memory cell 有权
标题翻译：多级，分闸，闪存单元
公开(公告)号：US06281545B1
公开(公告)日：2001-08-28
申请号：US09199130
申请日：1998-11-24
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L29788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

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