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91. 发明申请

US20100223426A1 Variable-width memory 有权
标题翻译：可变宽度内存
公开(公告)号：US20100223426A1
公开(公告)日：2010-09-02
申请号：US12631614
申请日：2009-12-04
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/02
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

92. 发明授权

US07660183B2 Low power memory device 有权
标题翻译：低功耗存储设备
公开(公告)号：US07660183B2
公开(公告)日：2010-02-09
申请号：US11194812
申请日：2005-08-01
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.
摘要翻译：在具有存储器核心和信号接口的存储器件中，接收指定存储器访问的至少一部分的命令。在存储器访问期间，在存储器核心和信令接口之间传送数据，并且在信令接口和外部信号路径之间传送数据，并且在信令接口和外部信号路径之间传送数据之前，接收使能信息选择性地启用至少第一存储器资源和第二存储器资源，其中第一存储器资源和第二存储器资源中的每一个执行与存储器访问相关联的控制功能。

93. 发明授权

US07577789B2 Upgradable memory system with reconfigurable interconnect 有权
标题翻译：具有可重构互连的可升级内存系统
公开(公告)号：US07577789B2
公开(公告)日：2009-08-18
申请号：US11388449
申请日：2006-03-24
申请人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G06F12/04
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译：描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。一个拓扑结构可编程，以支持轨到轨或半电源终端。另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。终端电压和阻抗也可能会被调整。

94. 发明申请

US20090138646A1 METHOD AND APPARATUS FOR SIGNALING BETWEEN DEVICES OF A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统的设备之间进行信号的方法和装置
公开(公告)号：US20090138646A1
公开(公告)日：2009-05-28
申请号：US12360780
申请日：2009-01-27
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/28
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
摘要翻译：提供了一种用于在存储器系统的设备之间进行信令的方法和装置。根据本发明的实施例，实现了几个能力中的一个或多个，以提供迄今为止无法达到的重要系统度量的水平，例如高性能和/或低成本。这些功能涉及定时调整能力，位时间调整能力，周期时间选择，对总线信号和/或时钟信号的差分和/或非差分信号的使用，以及在总线上使用终端结构，包括集成终端结构，以及主动控制电路，允许调整不同的特性总线阻抗和功率状态控制，包括优化终端值的校准过程，使用压摆率控制电路和传输特征控制电路在发射机模块的预驱动器和驱动器中，以允许调整不同的特性总线阻抗，并允许调整其他总线属性，包括优化这种电路的校准过程，和/或提供被设计为预先获取（预访问）字的存储器组件，其宽于数据总线的宽度，使得存储器访问带宽近似匹配传输带宽和备忘录 ry组件能够调整预取（预访问）字的大小，以适应与不同宽度的数据总线的连接。

95. 发明申请

US20090063887A1 MEMORY MODULE WITH TERMINATION COMPONENT 有权
标题翻译：具有终止组件的存储模块
公开(公告)号：US20090063887A1
公开(公告)日：2009-03-05
申请号：US12111816
申请日：2008-04-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F1/08
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译：一种具有第一和第二接口的存储器组件。提供第一接口以响应于第一时钟信号对地址信息进行采样。第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。

96. 发明授权

US07484064B2 Method and apparatus for signaling between devices of a memory system 有权
标题翻译：用于在存储器系统的设备之间进行信令的方法和装置
公开(公告)号：US07484064B2
公开(公告)日：2009-01-27
申请号：US10053340
申请日：2001-10-22
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
摘要翻译：提供了一种用于在存储器系统的设备之间进行信令的方法和装置。根据本发明的实施例，实现了几个能力中的一个或多个，以提供迄今为止无法达到的重要系统度量的水平，例如高性能和/或低成本。这些功能涉及定时调整能力，位时间调整能力，周期时间选择，对总线信号和/或时钟信号的差分和/或非差分信号的使用，以及在总线上使用终端结构，包括集成终端结构，以及主动控制电路，允许调整不同的特性总线阻抗和功率状态控制，包括优化终端值的校准过程，使用压摆率控制电路和传输特征控制电路在发射机模块的预驱动器和驱动器中，以允许调整不同的特性总线阻抗，并允许调整其他总线属性，包括优化这种电路的校准过程，和/或提供被设计为预先获取（预访问）字的存储器组件，其宽于数据总线的宽度，使得存储器访问带宽近似匹配传输带宽和备忘录 ry组件能够调整预取（预访问）字的大小，以适应与不同宽度的数据总线的连接。

97. 发明申请

US20080140974A1 LOW POWER MEMORY DEVICE 有权
标题翻译：低功率存储器件
公开(公告)号：US20080140974A1
公开(公告)日：2008-06-12
申请号：US12018489
申请日：2008-01-23
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.
摘要翻译：在具有存储器核心和信号接口的存储器件中，接收指定存储器访问的至少一部分的命令。在存储器访问期间，在存储器核心和信令接口之间传送数据，以及在信令接口和外部信号路径之间传送数据，并且在信令接口和外部信号路径之间传送数据之前，接收使能信息选择性地启用至少第一存储器资源和第二存储器资源，其中第一存储器资源和第二存储器资源中的每一个执行与存储器访问相关联的控制功能。

98. 发明授权

US07200055B2 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US07200055B2
公开(公告)日：2007-04-03
申请号：US11219381
申请日：2005-09-01
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory device. A second signal lines is coupled to the second memory device and dedicated to data transfers involving the second memory device. A third set of signal lines is coupled to the first and second memory devices and the termination component such that a signal propagating on the third set of signal lines propagates past the first memory device before reaching the second memory device, and propagates past the second memory device before reaching the termination component.
摘要翻译：一种具有端接部件的存储器模块。存储器模块包括第一和第二存储器件，终端元件和三组信号线。第一组信号线耦合到第一存储器设备，并专用于涉及第一存储器件的数据传输。第二信号线耦合到第二存储器设备，并专用于涉及第二存储器件的数据传输。第三组信号线耦合到第一和第二存储器件和端接部件，使得在第三组信号线传播的信号在到达第二存储器件之前传播通过第一存储器件，并且传播通过第二存储器设备到达终端组件之前。

99. 发明授权

US07177998B2 Method, system and memory controller utilizing adjustable read data delay settings 有权
标题翻译：方法，系统和存储器控制器利用可调读数据延迟设置
公开(公告)号：US07177998B2
公开(公告)日：2007-02-13
申请号：US11335029
申请日：2006-01-18
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/20
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
摘要翻译：使用可调读数据延迟设置的方法，系统和内存控制器。存储器控制器包括控制发射电路，数据接收电路和定时电路。控制电路通过共享控制信号路径将控制信号发送到多个存储器件。数据接收电路经由相应的数据信号路径从存储器件接收数据信号。定时电路延迟每个数据信号路径上的数据信号的接收相应的时间间隔，该时间间隔至少部分地基于控制信号在从存储器控制器到控制信号路径的传播所需的时间相应的一个存储器件。

100. 发明授权

US06675272B2 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于在不同位置的存储器组件之间协调存储器操作的方法和装置
公开(公告)号：US06675272B2
公开(公告)日：2004-01-06
申请号：US09841911
申请日：2001-04-24
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F1200
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译：描述了用于协调不同位置的存储器组件之间的存储器操作的方法和装置。根据本发明的实施例，为耦合到多个存储器组件的地址总线实现波浪流水线化。多个存储器组件根据与地址总线传播延迟和数据总线传播延迟有关的坐标进行配置。与复制这些信号的传播延迟的地址和/或控制信号相关联的定时信号用于协调存储器操作。

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