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91. 发明授权

US07224029B2 Method and structure to create multiple device widths in FinFET technology in both bulk and SOI 有权
标题翻译： FinFET技术在体和SOI中产生多个器件宽度的方法和结构
公开(公告)号：US07224029B2
公开(公告)日：2007-05-29
申请号：US10707964
申请日：2004-01-28
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/36 , H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L29/66795 , H01L29/66803
摘要： Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.
摘要翻译：公开了一种用于制造在衬底上具有掩埋氧化层的鳍式场效应晶体管（FinFET）的结构和方法，至少一个第一鳍结构和位于掩埋氧化物层上的至少一个第二鳍结构。第一间隔件与第一翅片结构相邻，第二间隔件邻近第二翅片结构。当与由第二间隔物覆盖的第二鳍结构的部分相比时，第一间隔物覆盖第一鳍结构的较大部分。具有较大间隔物的那些翅片将接收较小的半导体掺杂面积，并且具有较小间隔物的那些翅片将接收更大面积的半导体掺杂。因此，由不同尺寸的间隔件引起的第一散热片和第二散热片之间的掺杂存在差异。与第一鳍片相比，第一鳍片和第二鳍片之间的掺杂差异改变了第二鳍片的有效宽度。

92. 发明授权

US07188322B2 Circuit layout methodology using a shape processing application 失效
标题翻译：使用形状处理应用的电路布局方法
公开(公告)号：US07188322B2
公开(公告)日：2007-03-06
申请号：US10906591
申请日：2005-02-25
申请人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
发明人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

93. 发明授权

US07132325B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
公开(公告)号：US07132325B2
公开(公告)日：2006-11-07
申请号：US10731511
申请日：2003-12-09
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L21/8242
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

94. 发明授权

US07112845B2 Double gate trench transistor 失效
公开(公告)号：US07112845B2
公开(公告)日：2006-09-26
申请号：US10064171
申请日：2002-06-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66818
摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

95. 发明授权

US06940130B2 Body contact MOSFET 失效
标题翻译：体接触MOSFET
公开(公告)号：US06940130B2
公开(公告)日：2005-09-06
申请号：US10687333
申请日：2003-10-16
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

96. 发明授权

US06812075B2 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same 有权
公开(公告)号：US06812075B2
公开(公告)日：2004-11-02
申请号：US10428705
申请日：2003-05-02
申请人： David M. Fried , Timothy J. Hoague , Edward J. Nowak , Jed H. Rankin
发明人： David M. Fried , Timothy J. Hoague , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2100
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78636
摘要： A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.

97. 发明授权

US06677645B2 Body contact MOSFET 有权
标题翻译：体接触MOSFET
公开(公告)号：US06677645B2
公开(公告)日：2004-01-13
申请号：US10061263
申请日：2002-01-31
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

98. 发明授权

US06624031B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
标题翻译：基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法
公开(公告)号：US06624031B2
公开(公告)日：2003-09-23
申请号：US09989850
申请日：2001-11-20
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.
摘要翻译：一种检测半导体工艺应力诱发缺陷的方法。该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管。二极管可代替DRAM单元。还公开了使用二极管作为反熔丝。

99. 发明授权

US06610607B1 Method to define and tailor process limited lithographic features using a modified hard mask process 有权
标题翻译：使用改进的硬掩模工艺定义和定制工艺有限的光刻特征的方法
公开(公告)号：US06610607B1
公开(公告)日：2003-08-26
申请号：US09578362
申请日：2000-05-25
申请人： Douglas S. Armbrust , Dale W. Martin , Jed H. Rankin , Sylvia Tousley
发明人： Douglas S. Armbrust , Dale W. Martin , Jed H. Rankin , Sylvia Tousley
IPC分类号： H01L21461
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.
摘要翻译：提供了一种定义和定制加工限制光刻特征的方法。该方法可用于在半导体晶片上的特征之间形成次光刻空间。在晶片上形成并图案化掩模。垫片形成在面罩的侧壁上。然后将掩模和间隔物的图案转移到下层。

100. 发明授权

US06583469B1 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same 有权
标题翻译： FinFET应用的自对准狗骨结构及其制造方法
公开(公告)号：US06583469B1
公开(公告)日：2003-06-24
申请号：US09683626
申请日：2002-01-28
申请人： David M. Fried , Timothy J. Hoague , Edward J. Nowak , Jed H. Rankin
发明人： David M. Fried , Timothy J. Hoague , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78636
摘要： A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.
摘要翻译：提供了具有自对准狗骨结构的垂直取向的FET及其制造方法。具体地，垂直取向的FET包括沟道区，源极区和漏极区。沟道区具有第一水平宽度，并且源区和漏区具有大于第一水平宽度的第二水平宽度。源极和漏极区域中的每一个具有与沟道区域邻接的具有从第一水平宽度到第二水平宽度基本线性地变化的水平宽度的锥形部分。

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