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1. 发明授权

US06770907B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
标题翻译：基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法
公开(公告)号：US06770907B2
公开(公告)日：2004-08-03
申请号：US10449426
申请日：2003-05-30
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.
摘要翻译：一种检测半导体工艺应力诱发缺陷的方法。该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管。 DRAM单元可以代替二极管。还公开了使用二极管作为反熔丝。

2. 发明授权

US07132325B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
公开(公告)号：US07132325B2
公开(公告)日：2006-11-07
申请号：US10731511
申请日：2003-12-09
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L21/8242
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

3. 发明授权

US06624031B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
标题翻译：基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法
公开(公告)号：US06624031B2
公开(公告)日：2003-09-23
申请号：US09989850
申请日：2001-11-20
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.
摘要翻译：一种检测半导体工艺应力诱发缺陷的方法。该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管。二极管可代替DRAM单元。还公开了使用二极管作为反熔丝。

4. 发明授权

US5734192A Trench isolation for active areas and first level conductors 失效
公开(公告)号：US5734192A
公开(公告)日：1998-03-31
申请号：US581680
申请日：1995-12-22
申请人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
发明人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
IPC分类号： H01L21/762 , H01L23/522 , H01L29/00
CPC分类号： H01L21/76224 , H01L23/5222 , H01L2924/0002
摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

5. 发明授权

US6063687A Formation of trench isolation for active areas and first level conductors 失效
标题翻译：形成有源区和一级导体的沟槽隔离
公开(公告)号：US6063687A
公开(公告)日：2000-05-16
申请号：US837141
申请日：1997-04-14
申请人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
发明人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
IPC分类号： H01L21/762 , H01L23/522 , H01L21/76
CPC分类号： H01L21/76224 , H01L23/5222 , H01L2924/0002
摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.
摘要翻译：提供了一种用于半导体的沟槽隔离结构，包括隔离环和隔离路径。隔离环围绕有源半导体区域，并且在非活性半导体区域的外部界定。隔离通道从隔离环延伸穿过非活性半导体区域。隔离路径上的第一级导体将有源半导体区域中的器件电连接或电容耦合到隔离环外部的衬底上的位置。隔离路径具有从导体的布局导出的配置。

6. 发明授权

US06394638B1 Trench isolation for active areas and first level conductors 失效
标题翻译：有源区和一级导体的沟槽隔离
公开(公告)号：US06394638B1
公开(公告)日：2002-05-28
申请号：US09560212
申请日：2000-04-28
申请人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
发明人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
IPC分类号： H01L21762
CPC分类号： H01L21/76224 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.
摘要翻译：提供了一种用于半导体的沟槽隔离结构，包括隔离环和隔离路径。隔离环围绕有源半导体区域，并且在非活性半导体区域的外部界定。隔离通道从隔离环延伸穿过非活性半导体区域。隔离路径上的第一级导体将有源半导体区域中的器件电连接或电容耦合到隔离环外部的衬底上的位置。隔离路径具有从导体的布局导出的配置。

7. 发明授权

US6147394A Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效
标题翻译：用一个掩模步骤和由此形成的自对准隔离结构光刻地限定三个区域的方法
公开(公告)号：US6147394A
公开(公告)日：2000-11-14
申请号：US172366
申请日：1998-10-14
申请人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
发明人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , H01L29/00
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.
摘要翻译：本发明的优选实施例提供了一种使用单个掩蔽步骤在半导体衬底上限定三个区域的方法。优选实施例使用光刻胶材料，同时具有曝光的正色调和负色调响应。这种材料的组合可以提供一种新型的抗蚀剂，我们称之为混合抗蚀剂。混合抗蚀剂包含作用于第一光化能级的正色调成分和以第二光化能级起作用的负色调成分，其中第一和第二光化能级被光化能的中间范围分隔。当混合抗蚀剂暴露于光化能时，受到完全曝光的抗蚀剂的区域交联以形成负色调线图案，未曝光形式的区域保持光活性并形成正色调图案，并且暴露于中间量的辐射在开发过程中变得可溶并被冲走。这暴露了掩码上的第一个区域。然后毯子暴露混合抗蚀剂，正色调图案变得可溶，并且在显影过程中将被洗掉。这掩盖了掩模上的第二区域，第三区域仍被混合抗蚀剂覆盖。因此，优选实施例能够使用单个掩蔽步骤来定义三个区域，而不会叠加错误。

8. 发明授权

US5972570A Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效
公开(公告)号：US5972570A
公开(公告)日：1999-10-26
申请号：US895748
申请日：1997-07-17
申请人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
发明人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , G03F7/26
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

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