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91. 发明授权

US07435676B2 Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity 失效
标题翻译：双镶嵌工艺流程可实现极少的ULK膜修饰和增强的堆叠完整性
公开(公告)号：US07435676B2
公开(公告)日：2008-10-14
申请号：US11328981
申请日：2006-01-10
申请人： Timothy J. Dalton , Nicholas C. Fuller , Satyanarayana V. Nitta
发明人： Timothy J. Dalton , Nicholas C. Fuller , Satyanarayana V. Nitta
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76808 , H01L21/76829
摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.
摘要翻译：本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂在灰化图案材料之前完成的阻挡层开口步骤。该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

92. 发明授权

US07405147B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US07405147B2
公开(公告)日：2008-07-29
申请号：US10707996
申请日：2004-01-30
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lines or vias.
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线或通孔上或附近形成间隙。

93. 发明授权

US07037744B2 Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby 失效
标题翻译：制造自对准纳米柱状空中桥梁的方法及由此制造的结构
公开(公告)号：US07037744B2
公开(公告)日：2006-05-02
申请号：US11150059
申请日：2005-06-10
申请人： Matthew E Colburn , Satyanarayana V Nitta , Sampath Purushothaman
发明人： Matthew E Colburn , Satyanarayana V Nitta , Sampath Purushothaman
IPC分类号： H01L21/00
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.
摘要翻译：一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开，光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。线路由固体或图案化的电介质特征支撑。该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。

94. 发明授权

US06911400B2 Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same 失效
公开(公告)号：US06911400B2
公开(公告)日：2005-06-28
申请号：US10287905
申请日：2002-11-05
申请人： Matthew E Colburn , Stephen M Gates , Jeffrey C Hedrick , Elbert Huang , Satyanarayana V Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew E Colburn , Stephen M Gates , Jeffrey C Hedrick , Elbert Huang , Satyanarayana V Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L21/027 , B32B3/00 , G03F7/00 , G03F7/16 , G03F7/26 , H01L21/31 , H01L21/3105 , H01L21/469
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

95. 发明授权

US06831366B2 Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer 有权
标题翻译：互连件包含由多孔掩埋蚀刻停止层隔开的第一和第二多孔低k电介质
公开(公告)号：US06831366B2
公开(公告)日：2004-12-14
申请号：US10396274
申请日：2003-03-25
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2352
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
摘要翻译：提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

96. 发明授权

US06831364B2 Method for forming a porous dielectric material layer in a semiconductor device and device formed 有权
标题翻译：在半导体器件中形成多孔介电材料层的方法和形成的器件
公开(公告)号：US06831364B2
公开(公告)日：2004-12-14
申请号：US10210173
申请日：2002-08-01
申请人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
发明人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
IPC分类号： H01L2352
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76828 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.
摘要翻译：公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层部分固化温度以将无孔电介质材料转变为多孔电介质材料，从而形成具有低介电常数（即小于2.6）的电介质材料。无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高固化温度下，第二相聚合物材料基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

97. 发明授权

US06734096B2 Fine-pitch device lithography using a sacrificial hardmask 失效
标题翻译：使用牺牲硬掩模的精细间距器件光刻
公开(公告)号：US06734096B2
公开(公告)日：2004-05-11
申请号：US10053288
申请日：2002-01-17
申请人： Timothy J. Dalton , Minakshisundaran B. Anand , Michael D. Armacost , Shyng-Tsong Chen , Stephen M. Gates , Stephen E. Greco , Simon M. Karecki , Satyanarayana V. Nitta
发明人： Timothy J. Dalton , Minakshisundaran B. Anand , Michael D. Armacost , Shyng-Tsong Chen , Stephen M. Gates , Stephen E. Greco , Simon M. Karecki , Satyanarayana V. Nitta
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76811 , H01L21/76826
摘要： A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.
摘要翻译：描述了在低介电常数衬底中形成金属图案的方法。准备了一个硬掩模，其包括低k较低的硬掩模层和顶部硬掩模层。顶部硬掩模层是厚度为约200埃的牺牲层，优选由耐火氮化物形成，并且在随后的CMP金属去除工艺中用作停止层。使用抗蚀剂层进行图案化。通过在硬掩模中形成保护层，或者通过使用非氧化抗蚀剂剥离工艺来避免对下部硬掩模层的氧化损伤。

98. 发明授权

US06677680B2 Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials 有权
标题翻译：混合低k互连结构由2个旋涂电介质材料组成
公开(公告)号：US06677680B2
公开(公告)日：2004-01-13
申请号：US09795429
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/02118 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/3124 , H01L21/76811
摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).
摘要翻译：提供了一种双镶嵌型金属布线加上低k电介质互连结构，其中导电金属线和通孔内置于混合低k电介质中，该电介质包括两个具有不同原子组成的旋转电介质和至少一个的两个旋转电介质是多孔的。用于形成本发明的混合低k电介质的两个旋转电介质各自具有约2.6或更小的介电常数，优选混合结构的每个电介质具有约1.2至约2.2的k。通过利用本发明的混合低k电介质，获得对金属线电阻（沟槽深度）的优异控制，而不增加成本。这是在没有使用掩埋蚀刻停止层的情况下实现的，如果存在的话，它将在两个旋转电介质之间形成。此外，混合低k电介质的旋转电介质具有明显不同的原子组成，使得能够使用底部纺丝电介质（即，通过电介质）控制导体电阻，作为用于上纺丝的固有蚀刻停止层电介质（即线电介质）。

99. 发明授权

US06451712B1 Method for forming a porous dielectric material layer in a semiconductor device and device formed 有权
标题翻译：在半导体器件中形成多孔介电材料层的方法和形成的器件
公开(公告)号：US06451712B1
公开(公告)日：2002-09-17
申请号：US09739935
申请日：2000-12-18
申请人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
发明人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76828 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.
摘要翻译：公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层部分固化温度以将无孔电介质材料转化为多孔电介质材料，从而获得具有显着改善介电常数（即小于2.6）的电介质材料。无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高的固化温度下，第二相聚合物材料基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

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