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91. 发明授权

US08853819B2 Semiconductor structure with passive element network and manufacturing method thereof 有权
标题翻译：无源元网络的半导体结构及其制造方法
公开(公告)号：US08853819B2
公开(公告)日：2014-10-07
申请号：US13338087
申请日：2011-12-27
申请人： Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
发明人： Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
IPC分类号： H01L27/08 , H01L23/498 , H01L49/02 , H01L23/64 , H01L23/522 , H01L23/14 , H01L27/01 , H01L25/065 , H01L21/768 , H01L23/60
CPC分类号： H01L27/016 , H01L21/76898 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L23/5227 , H01L23/5228 , H01L23/60 , H01L23/64 , H01L25/0657 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/16 , H01L2225/06517 , H01L2225/06572 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.
摘要翻译：本发明涉及一种具有集成无源网络的半导体结构及其制造方法。半导体结构包括可以是插入件的衬底。衬底可以包括多个导电通孔。在各种实施例中，衬底包括设置在其上的电介质层，电介质层具有形成直孔的开口，允许无源网络和导电通孔之间的电连接。无源网络包括一系列图案化的电介质层和导电层，形成无源电子元件。在一个实施例中，无源器件包括耦合到一对电感器的公共电阻器，每个电感器耦合到电容器。在另一个实施例中，无源器件包括电阻器和电感器，它们彼此电连接，电感器的底表面与电阻器的底表面共面。

92. 发明授权

US08823166B2 Pillar bumps and process for making same 有权
标题翻译：支柱颠簸和制作过程
公开(公告)号：US08823166B2
公开(公告)日：2014-09-02
申请号：US12871565
申请日：2010-08-30
申请人： Cheng-Chung Lin , Chung-Shi Liu , Meng-Wei Chou , Kuo Cheng Lin , Wen-Hsiung Lu , Chien Ling Hwang , Ying-Jui Huang , De-Yuan Lu
发明人： Cheng-Chung Lin , Chung-Shi Liu , Meng-Wei Chou , Kuo Cheng Lin , Wen-Hsiung Lu , Chien Ling Hwang , Ying-Jui Huang , De-Yuan Lu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/11 , H01L21/02052 , H01L21/32125 , H01L21/76873 , H01L21/76885 , H01L23/488 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/1084 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05541 , H01L2224/05573 , H01L2224/1111 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11614 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/1191 , H01L2224/11912 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/81191 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01059 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0541 , H01L2924/07025 , H01L2924/10329 , H01L2924/14 , H01L2924/20102 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H01L2924/0105 , H01L2924/00014 , H01L2224/13099 , H01L2924/207
摘要： Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
摘要翻译：用于提供焊料柱凸块的装置和方法。通过在集成电路的端子上通过导电材料的电镀形成导电材料的支柱，在集成电路的输入/输出端子上形成支柱凸点连接。柱状凸块的基部具有比上部更大的宽度。柱形凸起的基部的横截面可以形成梯形，矩形或倾斜的形状。焊料可以形成在柱的顶表面上。所得到的焊料柱凸起形成比现有技术更可靠的细间距封装焊接连接。

93. 发明授权

US08822343B2 Enhanced FinFET process overlay mark 有权
标题翻译：增强型FinFET工艺叠加标记
公开(公告)号：US08822343B2
公开(公告)日：2014-09-02
申请号：US13602697
申请日：2012-09-04
申请人： Chi-Wen Hsieh , Chi-Kang Chang , Chia-Chu Liu , Meng-Wei Chen , Kuei-Shun Chen
发明人： Chi-Wen Hsieh , Chi-Kang Chang , Chia-Chu Liu , Meng-Wei Chen , Kuei-Shun Chen
IPC分类号： H01L21/308
CPC分类号： H01L23/544 , G03F7/70633 , G03F7/70683 , H01L27/0883 , H01L27/0886 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
摘要翻译：公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。在基板上形成一个或多个电介质层和硬掩模。图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。间隔物形成在图案化的硬掩模层上。垫片进一步限定重叠标记鳍片和有源器件鳍片。覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

94. 发明授权

US08753937B2 Manufacturing method of power transistor device with super junction 失效
标题翻译：具有超级结的功率晶体管器件的制造方法
公开(公告)号：US08753937B2
公开(公告)日：2014-06-17
申请号：US13553806
申请日：2012-07-19
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L21/8236
CPC分类号： H01L21/26513 , H01L21/2255 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7802
摘要： The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.
摘要翻译：本发明提供一种功率晶体管器件的制造方法。首先，提供第一导电类型的半导体衬底，并且在半导体衬底中形成至少一个沟槽。接下来，沟槽填充有掺杂剂源层，并且执行第一热驱入工艺以在半导体衬底中形成第二导电类型的两个掺杂扩散区，其中每个掺杂扩散区的掺杂浓度接近沟槽不同于远离沟槽的每个掺杂扩散区域中的一个。然后，去除掺杂剂源层，并且执行倾斜角离子注入工艺和第二热驱入工艺以调节靠近沟槽的每个掺杂扩散区域的掺杂浓度。

95. 发明授权

US08716139B2 Method of patterning a semiconductor device 有权
标题翻译：图案化半导体器件的方法
公开(公告)号：US08716139B2
公开(公告)日：2014-05-06
申请号：US13409863
申请日：2012-03-01
申请人： George Liu , Kuei Shun Chen , Meng Wei Chen
发明人： George Liu , Kuei Shun Chen , Meng Wei Chen
IPC分类号： H01L21/32 , G03F7/00
CPC分类号： H01L21/0332
摘要： A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.
摘要翻译：一种图案化半导体器件的方法，包括将布局分为多于一种图案。该方法还包括在半导体衬底上沉积薄膜叠层，在薄膜叠层上沉积硬掩模，以及在硬掩模上沉积第一光致抗蚀剂。该方法还包括使用多于一种图案的第一图案来图案化第一光致抗蚀剂。该方法还包括蚀刻硬掩模以将多于一种图案的第一图案的设计转移到硬掩模。该方法还包括在蚀刻的硬掩模上沉积第二光致抗蚀剂并使用多于一种图案的第二图案来图案化第二光致抗蚀剂。该方法还包括蚀刻通过蚀刻的硬掩模和第二光致抗蚀剂的组合暴露的膜堆的部分。

96. 发明申请

US20130230980A1 PHOTORESIST STRUCTURES HAVING RESISTANCE TO PEELING 有权
标题翻译：具有抗剥离性的光电结构
公开(公告)号：US20130230980A1
公开(公告)日：2013-09-05
申请号：US13409863
申请日：2012-03-01
申请人： George LIU , Kuei Shun CHEN , Meng Wei CHEN
发明人： George LIU , Kuei Shun CHEN , Meng Wei CHEN
IPC分类号： H01L21/302
CPC分类号： H01L21/0332
摘要： A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.
摘要翻译：一种图案化半导体器件的方法，包括将布局分为多于一种图案。该方法还包括在半导体衬底上沉积薄膜叠层，在薄膜叠层上沉积硬掩模，以及在硬掩模上沉积第一光致抗蚀剂。该方法还包括使用多于一种图案的第一图案来图案化第一光致抗蚀剂。该方法还包括蚀刻硬掩模以将多于一种图案的第一图案的设计转移到硬掩模。该方法还包括在蚀刻的硬掩模上沉积第二光致抗蚀剂并使用多于一种图案的第二图案来图案化第二光致抗蚀剂。该方法还包括蚀刻通过蚀刻的硬掩模和第二光致抗蚀剂的组合暴露的膜堆的部分。

97. 发明申请

US20130210205A1 MANUFACTURING METHOD OF POWER TRANSISTOR DEVICE WITH SUPER JUNCTION 失效
标题翻译：具有超级连接的功率晶体管器件的制造方法
公开(公告)号：US20130210205A1
公开(公告)日：2013-08-15
申请号：US13553806
申请日：2012-07-19
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/2255 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7802
摘要： The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.
摘要翻译：本发明提供一种功率晶体管器件的制造方法。首先，提供第一导电类型的半导体衬底，并且在半导体衬底中形成至少一个沟槽。接下来，沟槽填充有掺杂剂源层，并且执行第一热驱入工艺以在半导体衬底中形成第二导电类型的两个掺杂扩散区，其中每个掺杂扩散区的掺杂浓度接近沟槽不同于远离沟槽的每个掺杂扩散区域中的一个。然后，去除掺杂剂源层，并且执行倾斜角离子注入工艺和第二热驱入工艺以调节靠近沟槽的每个掺杂扩散区域的掺杂浓度。

98. 发明授权

US08492221B2 Method for fabricating power semiconductor device with super junction structure 有权
标题翻译：具有超结结构的功率半导体器件的制造方法
公开(公告)号：US08492221B2
公开(公告)日：2013-07-23
申请号：US13433282
申请日：2012-03-28
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0886 , H01L29/456 , H01L29/66734
摘要： A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.
摘要翻译：提供一种制造功率半导体器件的方法。制备具有第一导电类型的衬底。在基板上形成具有第二导电类型的半导体层。在半导体层上形成至少具有开口的硬掩模图案。执行第一沟槽蚀刻以经由开口在半导体层中形成第一凹槽。执行第一离子注入以通过开口垂直地将掺杂剂注入第一凹槽的底部，从而形成第一掺杂区域。执行第二沟槽蚀刻以蚀刻穿过第一掺杂区域，从而形成第二凹槽。

99. 发明申请

US20130134487A1 POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有超级连接的功率晶体管器件及其制造方法
公开(公告)号：US20130134487A1
公开(公告)日：2013-05-30
申请号：US13541763
申请日：2012-07-04
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/105 , H01L29/1095 , H01L29/66712
摘要： The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.
摘要翻译：本发明提供一种功率晶体管器件，其具有包含衬底，第一外延层，第二外延层和第三外延层的超结的超级结。第一外延层设置在基板上，并且具有多个沟槽。沟槽被第二外延层填充，并且第二外延层的顶表面高于第一外延层的顶表面。第二外延层具有穿过第二外延层并设置在第一外延层上的多个通孔。第二外延层和第一外延层具有不同的导电类型。通孔用第三外延层填充，第三外延层与第一外延层接触。第三外延层和第一外延层具有相同的导电类型。

100. 发明授权

US08404531B2 Method for fabricating a power transistor 有权
标题翻译：功率晶体管的制造方法
公开(公告)号：US08404531B2
公开(公告)日：2013-03-26
申请号：US13349038
申请日：2012-01-12
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Yi-Chun Shih , Main-Gwo Chen
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Yi-Chun Shih , Main-Gwo Chen
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/2253 , H01L21/2255 , H01L29/0634 , H01L29/1095
摘要： A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.
摘要翻译：一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电型载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

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