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91. 发明授权

US07482599B2 Fluid ultraviolet sterilization system 有权
公开(公告)号：US07482599B2
公开(公告)日：2009-01-27
申请号：US11600608
申请日：2006-11-16
申请人： Jian Chen , Minyi Han
发明人： Jian Chen , Minyi Han
IPC分类号： C02F1/32 , B01D19/08 , G01N23/12
CPC分类号： C02F1/325 , C02F2201/004 , C02F2201/3225 , C02F2201/328 , C02F2209/42
摘要： The invention provides a fluid UV sterilization system capable of automatically and stably keeping the fluid level, which includes a channel, a UV lamp module group, an electrical controller and a mounting bracket for UV lamp module(s), each UV lamp module comprising a frame and a plurality of UV lamps, the orientation of the frame and the lamps is perpendicular to or forms an angle with the general flow direction in the channel. A baffle is provided on either or both of the upstream and downstream of at least one of the UV lamp module(s), and the bottom of the baffle extends to such an extent towards the bottom of the channel that it at least reaches within the effective radiation distance of the UV lamp module group towards the fluid surface. The fluid UV sterilization system according to the present invention can control the fluid level automatically and stably, and can be used for the sterilization of domestic sewage, industrial sewage, recycled water, tap water and other kinds of water.

92. 发明授权

US07470798B2 7,8-bicycloalkyl-chroman derivatives 有权
标题翻译： 7,8-双环烷基 - 苯并二氢吡喃衍生物
公开(公告)号：US07470798B2
公开(公告)日：2008-12-30
申请号：US10941121
申请日：2004-09-15
申请人： Bing Wang , Gail Walkinshaw , Jian Chen , Xianming Jin , Jiangao Song , Wei Zhang
发明人： Bing Wang , Gail Walkinshaw , Jian Chen , Xianming Jin , Jiangao Song , Wei Zhang
IPC分类号： C07D309/00
CPC分类号： A61K31/352 , A61K31/353 , A61K31/357 , A61K31/496 , A61K31/675 , A61K31/7048 , C07D295/096 , C07D311/58 , C07D311/70 , C07D311/74 , C07D311/94 , C07D319/08 , C07D405/06 , C07D405/12 , C07D405/14 , C07D409/04 , C07D417/06 , C07D417/12
摘要： 7,8-Bicyclic-chroman derivatives of Formula I: wherein the substituents are defined as in the specification or the pharmaceutically acceptable salts thereof, are disclosed. They are useful for the treatment of inflammatory disorders, neurodegenerative disorders and/or mitochondrial disorders. They are also useful in the manufacture of pharmaceutical formulations for the treatment of such conditions.
摘要翻译： 7,8-式I的双环 - 苯并二氢吡喃衍生物：其中取代基如说明书或其药学上可接受的盐所定义。它们可用于治疗炎性疾病，神经变性疾病和/或线粒体疾病。它们也可用于制备用于治疗这些病症的药物制剂。

93. 发明申请

US20080310242A1 SYSTEMS FOR PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY 有权
标题翻译：用于半导体存储器中可编程芯片使能和芯片地址的系统
公开(公告)号：US20080310242A1
公开(公告)日：2008-12-18
申请号：US11763292
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/88 , G11C5/04
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

94. 发明申请

US20080290394A1 GATE ELECTRODE FOR A NONVOLATILE MEMORY CELL 有权
标题翻译：用于非易失性存储单元的门电极
公开(公告)号：US20080290394A1
公开(公告)日：2008-11-27
申请号：US12121591
申请日：2008-05-15
申请人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
发明人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
摘要翻译：非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。根据另一实施例，非易失性存储单元的栅电极包括第一子层和第一子层上具有不同宽度的第二子层。

95. 发明授权

US07450435B2 Systems for comprehensive erase verification in non-volatile memory 有权
标题翻译：非易失性存储器中的全面擦除验证系统
公开(公告)号：US07450435B2
公开(公告)日：2008-11-11
申请号：US11316162
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

96. 发明申请

US20080240375A1 Method Of Processing Multiple Ring Back Tone In Voice Service Application Based On Sip Fork 审中-公开
标题翻译：基于Sip Fork的语音服务应用中多回铃音处理方法
公开(公告)号：US20080240375A1
公开(公告)日：2008-10-02
申请号：US11914467
申请日：2005-05-19
申请人： Jian Chen
发明人： Jian Chen
IPC分类号： H04M1/64
CPC分类号： H04L29/06027 , H04L65/1006 , H04L65/4007 , H04M3/42017 , H04M3/42093 , H04M3/58 , H04M7/0075
摘要： A signaling-based processing method is presented, which is based on the influence of early media (a ring back tone or a voice notice before a session is established) from multiple called participants on the calling participant in SIP FORK-based voice service, which ensures the calling participant not to receive early media of multiple called participants at the same time.
摘要翻译：提出了一种基于信令的处理方法，该方法基于来自基于SIP FORK的语音服务的呼叫参与者的多个被叫参与者的早期媒体（建立会话之前的回铃音或语音通知）的影响，其中确保呼叫参与者不要同时接收多个被叫参与者的早期媒体。

97. 发明授权

US07427328B2 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
标题翻译：大面积纳米大电子基板及其用途
公开(公告)号：US07427328B2
公开(公告)日：2008-09-23
申请号：US11602783
申请日：2006-11-21
申请人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence A. Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence A. Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
IPC分类号： B05C5/00 , B05B7/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
摘要翻译：描述了具有多个半导体器件的电子基片的方法和装置。在衬底上形成纳米线薄膜。纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。在纳米线的薄膜中限定多个半导体区域。在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

98. 发明申请

US20080194737A1 POLYMER AND METHOD FOR USING THE POLYMER FOR SOLUBILIZING NANOTUBES 有权
标题翻译：聚合物和使用聚合物溶解纳米颗粒的方法
公开(公告)号：US20080194737A1
公开(公告)日：2008-08-14
申请号：US11775633
申请日：2007-07-10
申请人： Jian Chen , Haiying Liu
发明人： Jian Chen , Haiying Liu
IPC分类号： C08L1/00
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/174 , C01B2202/02 , C08G61/02 , C08G61/122 , C08G61/124 , C08G61/126 , Y10T428/2918 , Y10T428/2975 , Y10T428/30
摘要： A new, non-wrapping approach to solubilize nanotubes, such as carbon nanotubes, in organic and inorganic solvents is provided. In accordance with certain embodiments, carbon nanotube surfaces are functionalized in a non-wrapping fashion by functional conjugated polymers that include functional groups for solubilizing such nanotubes. Various embodiments provide polymers that noncovalently bond with carbon nanotubes in a non-wrapping fashion. For example, various embodiments of polymers are provided that comprise a relatively rigid backbone that is suitable for noncovalently bonding with a carbon nanotube substantially along the nanotube's length, as opposed to about its diameter. In preferred polymers, the major interaction between the polymer backbone and the nanotube surface is parallel π-stacking. The polymers further comprise at least one functional extension from the backbone that are any of various desired functional groups that are suitable for solubilizing a carbon nanotube.
摘要翻译：提供了一种在有机和无机溶剂中溶解纳米管（例如碳纳米管）的新的非包裹方法。根据某些实施方案，碳纳米管表面通过包括用于溶解这种纳米管的官能团的官能共轭聚合物以非包裹形式进行官能化。各种实施方案提供以非包装方式非共价结合碳纳米管的聚合物。例如，提供聚合物的各种实施方案，其包含相对于其直径相反的适于与碳纳米管基本上沿着纳米管长度非共价键合的相对刚性的主链。在优选的聚合物中，聚合物主链和纳米管表面之间的主要相互作用是平行的π-堆叠。聚合物还包含至少一个来自主链的功能性延伸，其为适于溶解碳纳米管的各种所需官能团中的任何一种。

99. 发明授权

US07394692B2 Non-volatile semiconductor memory with large erase blocks storing cycle counts 有权
标题翻译：具有存储循环计数的大擦除块的非易失性半导体存储器
公开(公告)号：US07394692B2
公开(公告)日：2008-07-01
申请号：US11419696
申请日：2006-05-22
申请人： Jian Chen , Tomoharu Tanaka
发明人： Jian Chen , Tomoharu Tanaka
IPC分类号： G11C11/34 , G11C7/10 , G11C8/00
CPC分类号： G11C11/5635 , G06F11/1068 , G11C11/5621 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C16/349 , G11C2211/5641 , G11C2211/5646
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.
摘要翻译：在被分成具有存储在每个块中的多页用户数据的存储单元的单独可擦除块的快闪EEPROM系统中，每个块已经承受的擦除周期数的计数被存储在块内的一个位置中，如在仅一页的备用单元中或分布在多页的标题区之间。最初从被擦除的每个块读取包含块循环计数的页面，临时存储循环计数，擦除块，然后将更新的循环计数写回到块位置。然后根据需要将用户数据编程到块的各个页面中。用户数据优选地存储在每个存储器单元存储元件的多于两个状态中，在这种情况下，周期计数可以以加速擦除处理的方式以二进制存储，并且减少写入更新周期的擦除状态的干扰效应计数可以造成。可以与循环计数一起存储从周期计数中计算的纠错码，从而允许验证存储的循环计数。

100. 发明申请

US20080104550A1 COMPENSATING FOR LAYOUT DIMENSION EFFECTS IN SEMICONDUCTOR DEVICE MODELING 失效
标题翻译：补偿半导体器件建模中的布局尺寸效应
公开(公告)号：US20080104550A1
公开(公告)日：2008-05-01
申请号：US11537390
申请日：2006-09-29
申请人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
发明人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.
摘要翻译：一种方法包括接收与集成电路装置相关联的设计数据。集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。基于经调整的尺寸模拟集成电路器件。

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