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91. 发明申请

US20120083117A1 Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer 有权
标题翻译：形成硬化多孔电介质层的方法和制造具有硬化多孔介电层的半导体器件的方法
公开(公告)号：US20120083117A1
公开(公告)日：2012-04-05
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/314 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

92. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

93. 发明授权

US07846796B2 Semiconductor devices including buried bit lines 有权
标题翻译：半导体器件包括埋地位线
公开(公告)号：US07846796B2
公开(公告)日：2010-12-07
申请号：US12791692
申请日：2010-06-01
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other
摘要翻译：半导体器件包括半导体衬底上的多个沟道结构。具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

94. 发明申请

US20100240185A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100240185A1
公开(公告)日：2010-09-23
申请号：US12658520
申请日：2010-02-11
申请人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
发明人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/456 , H01L29/66666
摘要： A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.
摘要翻译：一种制造半导体器件的方法包括：通过蚀刻衬底形成用于形成掩埋型线的沟槽; 在沟槽的底部和沟槽的壁上分别形成第一和第二氧化层; 去除一部分第一氧化层和整个第二氧化层; 以及通过在去除所述第二氧化层的所述沟槽的壁上执行硅化物处理，在所述沟槽的壁上形成所述埋入式导线。结果，埋入式电线彼此绝缘。

95. 发明申请

US20100112772A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100112772A1
公开(公告)日：2010-05-06
申请号：US12460945
申请日：2009-07-27
申请人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
发明人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28123 , H01L21/28282
摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
摘要翻译：一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

96. 发明申请

US20100105198A1 Gate Electrode of semiconductor device and method of forming the same 审中-公开
标题翻译：半导体器件的栅电极及其形成方法
公开(公告)号：US20100105198A1
公开(公告)日：2010-04-29
申请号：US12458767
申请日：2009-07-22
申请人： Sang-woo Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Sang-woo Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11568
摘要： A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.
摘要翻译：形成半导体器件的栅电极的方法包括在衬底的外围电路区域中形成第一多晶硅层，在第一多晶硅层上形成阻挡层，阻挡层提供欧姆接触，形成包括隧道绝缘层，电荷存储层和隔离绝缘层，在所述衬底的存储单元区域中，在所述阻挡层和所述阻挡绝缘层上形成第二多晶硅层，并且将所述第二多晶硅层硅化并形成硅化物栅极电极。

97. 发明申请

US20090101984A1 Semiconductor device having gate electrode including metal layer and method of manufacturing the same 审中-公开
标题翻译：具有包括金属层的栅电极的半导体器件及其制造方法
公开(公告)号：US20090101984A1
公开(公告)日：2009-04-23
申请号：US12003144
申请日：2007-12-20
申请人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
发明人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28247
摘要： A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film.
摘要翻译：半导体器件可以包括在半导体衬底和/或栅电极上的栅极电介质膜。栅电极可以包括依次层叠在栅极电介质膜上的第一金属膜，第一金属硅化物膜和/或导电多晶硅膜。

98. 发明申请

US20080200031A1 Method of fabricating gate electrode having polysilicon film and wiring metal film 审中-公开
标题翻译：制造具有多晶硅膜和布线金属膜的栅电极的方法
公开(公告)号：US20080200031A1
公开(公告)日：2008-08-21
申请号：US12007999
申请日：2008-01-18
申请人： Jang-hee Lee , Tae-ho Cha , Hae-sook Park , Gil-heyun Choi , Byung-hee Kim
发明人： Jang-hee Lee , Tae-ho Cha , Hae-sook Park , Gil-heyun Choi , Byung-hee Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78
摘要： A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer.
摘要翻译：根据示例实施例的形成半导体器件的栅电极的方法，其可以包括在半导体衬底上形成多晶硅膜。可以通过多次重复单位周期在多晶硅膜上形成界面控制层。单元循环可以包括形成界面金属膜并氮化界面金属膜的上表面部分以在界面金属膜的上表面部分上形成界面金属氮化物膜。可以在界面控制层上形成布线金属膜。

99. 发明申请

US20070099365A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070099365A1
公开(公告)日：2007-05-03
申请号：US11586610
申请日：2006-10-26
申请人： Dong-Chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
发明人： Dong-Chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
IPC分类号： H01L21/8234
CPC分类号： H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4941 , H01L29/517 , H01L29/518 , H01L29/6656
摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.
摘要翻译：半导体器件的集成电路具有不易发生严重RC延迟的线型图案。该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。集成电路可以构成半导体器件的栅极线。集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

100. 发明申请

US20070075313A1 Flat panel display device 有权
标题翻译：平板显示设备
公开(公告)号：US20070075313A1
公开(公告)日：2007-04-05
申请号：US11529470
申请日：2006-09-29
申请人： Won-Kyu Kwak , Byung-Hee Kim , Sang-Won Lee , In-Young Jung , Myung-Sup Kim
发明人： Won-Kyu Kwak , Byung-Hee Kim , Sang-Won Lee , In-Young Jung , Myung-Sup Kim
IPC分类号： H01L29/04
CPC分类号： H01L27/124 , H01L27/3276
摘要： A flat panel display device that includes a clad unit that may prevent terminals of a pad unit from becoming corroded or damaged by an etching solution during etching. The flat panel display device may include a display unit, a pad unit which may include a plurality of terminals electrically connecting the display unit to external devices, and a clad unit which may cover at least side end portions of the terminals, in which the clad unit may be composed of an insulating material.
摘要翻译：一种平板显示装置，包括可以防止焊盘单元的端子在蚀刻期间被蚀刻溶液腐蚀或损坏的包层单元。平板显示装置可以包括显示单元，可以包括将显示单元电连接到外部设备的多个端子的焊盘单元和可以覆盖端子的至少侧端部的包层单元，其中，单元可以由绝缘材料构成。

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