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1. 发明授权

US08294485B2 Detecting asymmetrical transistor leakage defects 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US08294485B2
公开(公告)日：2012-10-23
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： G01R31/02 , G01R31/08
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.
摘要翻译：检测大晶体管阵列（例如大量SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如，SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。

2. 发明授权

US08108803B2 Geometry based electrical hotspot detection in integrated circuit layouts 有权
标题翻译：集成电路布局中基于几何的电热点检测
公开(公告)号：US08108803B2
公开(公告)日：2012-01-31
申请号：US12603594
申请日：2009-10-22
申请人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
发明人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/16
摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.
摘要翻译：集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

3. 发明申请

US20110099529A1 GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS 有权
标题翻译：集成电路中基于几何的电气检测
公开(公告)号：US20110099529A1
公开(公告)日：2011-04-28
申请号：US12603594
申请日：2009-10-22
申请人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
发明人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/16
摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.
摘要翻译：集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

4. 发明申请

US20100201376A1 DETECTING ASYMMETRICAL TRANSISTOR LEAKAGE DEFECTS 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US20100201376A1
公开(公告)日：2010-08-12
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： H01H31/12
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifesting themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. The test array(s) is (are) disposed side-by-side with the “normal” array(s) on the same reticle so that process variations that affect the normal array will also affect the test array. The contact and metallization layers for the test array are adapted to connect groups (sub-blocks) of transistors together in parallel for leakage testing. The group size is chosen to ensure that the leakage current associated with a single defective transistor is significantly greater than the aggregate leakage current associated with all of non-defective transistors in the group. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements. The sub-blocks (groups) may be tested one at a time using a sub-block selection decoder to select the sub-block being tested.
摘要翻译：检测大晶体管阵列（例如大型SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。测试阵列与同一分划板上的“正常”阵列并排设置，从而影响正常阵列的过程变化也会影响测试阵列。用于测试阵列的接触和金属化层适于将晶体管的组（子块）并联连接在一起用于泄漏测试。选择组尺寸以确保与单个缺陷晶体管相关联的漏电流明显大于与组中的所有无缺陷晶体管相关的总漏电流。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。可以使用子块选择解码器一次一个地测试子块（组），以选择被测试的子块。

5. 发明申请

US20090119357A1 ADVANCED CORRELATION AND PROCESS WINDOW EVALUATION APPLICATION 审中-公开
标题翻译：先进的关联和过程窗口评估应用
公开(公告)号：US20090119357A1
公开(公告)日：2009-05-07
申请号：US11934914
申请日：2007-11-05
申请人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
发明人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
IPC分类号： G06F17/15
CPC分类号： G06K9/6253
摘要： A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form of a table and comprises independent variables. The method automatically joins the dependent variable table and the independent variable data to create a joint table. Then, the method can automatically perform a statistical analysis of the joint table to find correlations between the dependent variables and the independent variables and output the correlations, without requiring the user to input or identify the independent variables.
摘要翻译：方法只有用户输入（或选择）数据类型，报告键，因变量表和/或过滤限制。使用该信息，该方法根据数据类型和报告密钥自动定位独立的变量数据。这个独立的变量数据可以是一个表格的形式，并且包括自变量。该方法自动连接因变量表和独立变量数据以创建联合表。然后，该方法可以自动执行联合表的统计分析，以找出因变量和独立变量之间的相关性，并输出相关性，而不需要用户输入或识别自变量。

6. 发明授权

US08368069B2 Antifuse structure for in line circuit modification 有权
公开(公告)号：US08368069B2
公开(公告)日：2013-02-05
申请号：US13360270
申请日：2012-01-27
申请人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

7. 发明申请

US20120184075A1 REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION 失效
标题翻译：通过目标碳植入减少半导体器件中的分离形成
公开(公告)号：US20120184075A1
公开(公告)日：2012-07-19
申请号：US13009020
申请日：2011-01-19
申请人： Anthony G. Domenicucci , Shreesh Narasimha , Karen A. Nummy , Viorel C. Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Shreesh Narasimha , Karen A. Nummy , Viorel C. Ontalus , Yun-Yu Wang
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
摘要翻译：形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。这消除了导致设备泄漏失败的缺陷。

8. 发明授权

US07790599B2 Metal cap for interconnect structures 有权
标题翻译：用于互连结构的金属盖
公开(公告)号：US07790599B2
公开(公告)日：2010-09-07
申请号：US11734958
申请日：2007-04-13
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76843 , H01L21/76849
摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.
摘要翻译：描述了形成用于互连结构的改进的金属帽的结构和方法。该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

9. 发明申请

US20100025819A1 PROGRAMMABLE PRECISION RESISTOR AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：可编程精度电阻器及其编程方法
公开(公告)号：US20100025819A1
公开(公告)日：2010-02-04
申请号：US12185375
申请日：2008-08-04
申请人： Anthony G. Domenicucci , Terence L. Kane , Michael Tenney , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Terence L. Kane , Michael Tenney , Yun-Yu Wang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.
摘要翻译：第一电极和第二电极之间的连接部分包括半导体连接部分和包括第一金属半导体合金的金属半导体合金连接部分。电脉冲将整个连接部分转换成具有比第一金属半导体合金低的金属浓度的第二金属半导体合金。由于第一和第二金属半导体合金之间的化学计量差异，链接部分在编程之后具有比编程之前更高的电阻。良好控制的电阻的偏移，其有利地用作可编程精密电阻器。

10. 发明授权

US07569475B2 Interconnect structure having enhanced electromigration reliability and a method of fabricating same 有权
标题翻译：具有增强的电迁移可靠性的互连结构及其制造方法
公开(公告)号：US07569475B2
公开(公告)日：2009-08-04
申请号：US11560044
申请日：2006-11-15
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
摘要翻译：提供了具有改进的电迁移（EM）可靠性的互连结构。本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散屏障相邻。在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

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