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1. 发明授权

US07605609B1 Programmable level shifter 有权
标题翻译：可编程电平转换器
公开(公告)号：US07605609B1
公开(公告)日：2009-10-20
申请号：US11957598
申请日：2007-12-17
申请人： William B. Andrews , Mou C. Lin , John Schadt
发明人： William B. Andrews , Mou C. Lin , John Schadt
IPC分类号： H03K19/0175
CPC分类号： H03K3/356165
摘要： In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.
摘要翻译：在本发明的一个实施例中，可编程电平转换器可被选择性地配置为以高速模式或低功率模式工作。在两种模式中，电平移位器将一个电源域中的输入信号转换为另一个电源域中的输出信号。在高速模式中，p型器件被配置为电流镜放大器，为电平转换器提供相对较快的开关速度。在低功耗模式中，相同的p型器件被配置为交叉耦合的锁存器，其为电平移位器提供相对较低的功耗。选择性使能的n型器件提供具有较大有效n型器件的低功耗模式，以在低功耗模式下翻转由p型器件形成的交叉耦合锁存器。

2. 发明授权

US07586325B1 Integrated circuit having independent voltage and process/temperature control 有权
标题翻译：具有独立电压和工艺/温度控制的集成电路
公开(公告)号：US07586325B1
公开(公告)日：2009-09-08
申请号：US11949130
申请日：2007-12-03
申请人： William B. Andrews , Mou C. Lin , John Schadt
发明人： William B. Andrews , Mou C. Lin , John Schadt
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00369 , H03K17/14 , H03K19/17748 , H03K19/1778
摘要： In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage. In one implementation, the application circuitry is an output driver having source and sink driver blocks, where driver-control circuitry controls the configuration of the source driver block based on the selected output-driver power supply voltage, a source PT-control signal, and a selected drive strength, while controlling the configuration of the sink driver block based on the selected output-driver power supply voltage, a sink PT-control signal, and a selected drive strength.
摘要翻译：在一个实施例中，集成电路具有可操作的多个可用电源电压中的任何一个的可配置应用电路。以PT参考电压工作的PT控制电路产生指示过程和温度变化的PT控制信号。应用控制电路基于用于应用电路和PT控制信号的所选择的电源电压控制应用电路的配置，其中所选择的电源电压独立于PT参考电压。在一个实现中，应用电路是具有源和接收器驱动器块的输出驱动器，其中驱动器控制电路基于所选择的输出驱动器电源电压来控制源极驱动器模块的配置，源PT控制信号和选择的驱动强度，同时基于所选择的输出驱动器电源电压，信宿PT控制信号和选择的驱动强度来控制接收器驱动器块的配置。

3. 发明授权

US07262630B1 Programmable termination for single-ended and differential schemes 有权
标题翻译：单端和差分方案的可编程终端
公开(公告)号：US07262630B1
公开(公告)日：2007-08-28
申请号：US11194356
申请日：2005-08-01
申请人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
发明人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
IPC分类号： H03K19/003
CPC分类号： H03K19/17744 , H04L25/0278
摘要： In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.
摘要翻译：在本发明的一个实施例中，可编程终端结构具有用于相应焊盘的第一和第二终端电路以及它们之间的可编程连接。第一终端电路支持第一和第二组终端方案。共享电阻是每组中至少一个终端方案的一部分。第一终端电路支持第一焊盘和连接到片上电容器的用户定义节点之间的终止方案，使得第一焊盘通过端接方案连接到片上电容器。控制电路自动打开和关闭由第一终端电路支持的用于双向信令的终止方案，其中（1）如果输出缓冲器被配置为在第一焊盘处呈现输出信号，则控制电路关闭终止方案，（2）如果禁止输出缓冲器以便终止在第一焊盘处接收到的输入信号，则控制电路接通终止方案。

4. 发明授权

US07215149B1 Interface circuitry for electrical systems 有权
标题翻译：电气系统接口电路
公开(公告)号：US07215149B1
公开(公告)日：2007-05-08
申请号：US11012550
申请日：2004-12-15
申请人： William B. Andrews , Larry R. Fenstermaker , John Schadt , Mou C. Lin
发明人： William B. Andrews , Larry R. Fenstermaker , John Schadt , Mou C. Lin
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384 , H03K3/356104 , H03K19/018521
摘要： An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.
摘要翻译：电气系统具有主电路和接口（I / F）电路。主电路产生主输出信号。 I / F电路接收I / F输入信号和标志信号，并产生用于应用于从电路的I / F输出信号，其中I / F输入信号基于主输出信号，并且接口电路产生依赖于或独立于I / F输入信号的L / F输出信号，如标志信号所示。

5. 发明授权

US06943582B1 Programmable I/O structure for FPGAs and the like having shared circuitry 有权
标题翻译：具有共享电路的FPGA等的可编程I / O结构
公开(公告)号：US06943582B1
公开(公告)日：2005-09-13
申请号：US10671363
申请日：2003-09-25
申请人： William B. Andrews , Mou C. Lin , John Schadt
发明人： William B. Andrews , Mou C. Lin , John Schadt
IPC分类号： H03K19/177
CPC分类号： H03K19/17744
摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时，垫）。

6. 发明授权

US07495467B2 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07495467B2
公开(公告)日：2009-02-24
申请号：US11300886
申请日：2005-12-15
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及被设计成控制每个端接方案用于处理电压的校准电路，和温度（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

7. 发明授权

US07714608B1 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07714608B1
公开(公告)日：2010-05-11
申请号：US12370039
申请日：2009-02-12
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及设计成控制处理，电压和温度的每个端接方案的校准电路（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

8. 发明授权

US07443192B1 Output buffer with digital slew control 有权
标题翻译：输出缓冲器，带数字转换控制
公开(公告)号：US07443192B1
公开(公告)日：2008-10-28
申请号：US11643288
申请日：2006-12-21
申请人： William B. Andrews , Mou C. Lin , John A. Schadt
发明人： William B. Andrews , Mou C. Lin , John A. Schadt
IPC分类号： H03K19/003
CPC分类号： H03K19/00369
摘要： An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.
摘要翻译：一种改进的输出缓冲器，具有数字输出摆幅控制和补偿制造工艺变化。输出回转是通过将数字驱动信号排列成并联的输出晶体管来实现的。在一个实施例中，预驱动器通过使用串行数字逻辑门的传播延迟来排序驱动信号，以减少电源下降和/或地面反弹。输出晶体管基本上同时截止，以避免在输出缓冲器改变状态时不期望的电源DC电流流动。可编程地配置可以在任何给定时间导通的并联晶体管的数量允许用户补偿制造工艺变化并确定缓冲器的输出阻抗/驱动能力。

9. 发明授权

US07547995B1 Dynamic over-voltage protection scheme for interface circuitry 有权
标题翻译：接口电路的动态过压保护方案
公开(公告)号：US07547995B1
公开(公告)日：2009-06-16
申请号：US11345713
申请日：2006-02-02
申请人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
发明人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
IPC分类号： H01H9/54
CPC分类号： H03K19/00315 , Y10T307/944
摘要： In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.
摘要翻译：在本发明的一个实施例中，集成器件具有接口电路，该接口电路包括监视（至少）两个不同电源之间的相对电位的动态监视器，以使器件能够对过电压条件作出反应，从而可以进行适当的选择为接口电路中的不同组件选择哪个电源，例如输出驱动器和输入接收器。动态监视器可以在设备配置之前自动实现过电压保护，例如在设备通电状态期间。

10. 发明授权

US07230810B1 Dynamic over-voltage protection scheme for integrated-circuit devices 有权
标题翻译：集成电路器件的动态过压保护方案
公开(公告)号：US07230810B1
公开(公告)日：2007-06-12
申请号：US11007954
申请日：2004-12-09
申请人： William B. Andrews , Mou C. Lin , Larry R. Fenstermaker
发明人： William B. Andrews , Mou C. Lin , Larry R. Fenstermaker
IPC分类号： H02H9/04
CPC分类号： H01L27/0285
摘要： An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.
摘要翻译：具有晶体管器件和过电压保护电路的集成电路。晶体管器件以具有指定工作电压范围的技术实现，该晶体管器件具有栅极，漏极，源极和源极节点以及具有指定最大电压的规定工作电压范围。过电压保护电路分别适用于门和电池的电压。如果施加到至少一个漏极和源极节点的至少一个沟道电压超过规定的最大电压，则过电压保护电路控制栅极电压和电池电压中的至少一个以抑制一个或多个不利影响晶体管器件。

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