专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07473629B2 Substrate structure having a solder mask and a process for making the same 有权
标题翻译：具有焊接掩模的基板结构及其制造方法
公开(公告)号：US07473629B2
公开(公告)日：2009-01-06
申请号：US11634059
申请日：2006-12-06
申请人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
发明人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L21/44
CPC分类号： H05K3/3452 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H05K3/284 , H05K2203/0588 , H01L2924/00014 , H01L2924/00
摘要： A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
摘要翻译：一种具有焊料掩模的衬底结构及其制造方法，包括：（a）提供具有顶表面的衬底，所述顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。衬底结构可用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

2. 发明申请

US20070243704A1 Substrate structure having a solder mask and a process for making the same 有权
标题翻译：具有焊接掩模的基板结构及其制造方法
公开(公告)号：US20070243704A1
公开(公告)日：2007-10-18
申请号：US11634059
申请日：2006-12-06
申请人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
发明人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L21/44
CPC分类号： H05K3/3452 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H05K3/284 , H05K2203/0588 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
摘要翻译：本发明涉及一种具有焊接掩模的基片结构及其制造方法。该方法包括：（a）提供具有顶表面的基底，顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。由此，本发明的基板结构可以用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

3. 发明授权

US07511366B2 Multi-row substrate strip and method for manufacturing the same 有权
标题翻译：多行基板条及其制造方法
公开(公告)号：US07511366B2
公开(公告)日：2009-03-31
申请号：US11258085
申请日：2005-10-26
申请人： Yao-Ting Huang , Kuang-Lin Lo
发明人： Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L23/02
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/565 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： A multi-row substrate strip mainly includes a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer includes a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.
摘要翻译：多排衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。连接杆用于连接第一基板单元并连接第二基板单元。脱金属层包括连接杆上的多个流道部分，多个第一栅极部分和多个第二栅极部分。第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。

4. 发明申请

US20060091533A1 Multi-row substrate strip and method for manufacturing the same 有权
标题翻译：多行基板条及其制造方法
公开(公告)号：US20060091533A1
公开(公告)日：2006-05-04
申请号：US11258085
申请日：2005-10-26
申请人： Yao-Ting Huang , Kuang-Lin Lo
发明人： Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/565 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： A multi-row substrate strip mainly comprises a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer comprises a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.
摘要翻译：多列衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。连接杆用于连接第一基板单元并连接第二基板单元。脱金属层包括在连接杆上的多个流道部分，多个第一浇口部分和多个第二浇口部分。第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。

5. 发明授权

US08035820B2 Method and apparatus for resonant frequency identification through out-of-plane displacement detection 有权
标题翻译：用于通过面外位移检测进行谐振频率识别的方法和装置
公开(公告)号：US08035820B2
公开(公告)日：2011-10-11
申请号：US12837419
申请日：2010-07-15
申请人： Liang-Chia Chen , Chung-Chu Chang , Yao-Ting Huang , Jin-Liang Chen
发明人： Liang-Chia Chen , Chung-Chu Chang , Yao-Ting Huang , Jin-Liang Chen
IPC分类号： G01B11/02
CPC分类号： G01B11/161
摘要： A method for out-of-plane displacement detection is disclosed. The out-of-plane displacement is detected by analyzing all the fringe density indexes calculated using the frequency-domain information extracted from a series of interference images of the sample vibrating at different frequencies. The present invention further discloses a method and an apparatus for resonant frequency identification by detecting the peak value of all the fringe indexes calculated at different scanning frequencies. With the identified resonant frequency, the full-field vibratory surface profile of the sample in various resonance modes can be reconstructed.
摘要翻译：公开了一种用于面外位移检测的方法。通过分析使用从不同频率振动的样本的一系列干涉图像提取的频域信息计算出的所有边缘密度指数来检测面外位移。本发明还公开了一种通过检测在不同扫描频率下计算出的所有条纹指数的峰值的方法和装置，用于共振频率识别。利用所识别的共振频率，可以重建样品在各种谐振模式下的全场振动表面轮廓。

6. 发明授权

US07312105B2 Leadframe of a leadless flip-chip package and method for manufacturing the same 有权
标题翻译：无引脚倒装芯片封装的引线框及其制造方法
公开(公告)号：US07312105B2
公开(公告)日：2007-12-25
申请号：US11147918
申请日：2005-06-08
申请人： Yao-Ting Huang , Chih-Huang Chang
发明人： Yao-Ting Huang , Chih-Huang Chang
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L23/49861 , H01L23/3121 , H01L25/0657 , H01L2224/16225 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2924/00
摘要： A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.
摘要翻译：无引脚倒装芯片封装的引线框架包括多个内引线，非导电油墨层和焊接掩模层。内引线具有多个凸起连接端子，多个外部端子和多个再分配引线部分。在再分配引线部分的下表面上形成半蚀刻凹陷，并且填充有非导电油墨层。非导电油墨层将再分配引线部分固定到凸块连接端子上。焊接掩模层容易地形成在非导电油墨层上并覆盖内部引线。

7. 发明申请

US20050287701A1 Leadframe for a multi-chip package and method for manufacturing the same 有权
标题翻译：一种多芯片封装的引线框及其制造方法
公开(公告)号：US20050287701A1
公开(公告)日：2005-12-29
申请号：US11138491
申请日：2005-05-27
申请人： Yao-Ting Huang
发明人： Yao-Ting Huang
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/495 , H01L23/538 , H01L25/065 , H01L25/16
CPC分类号： H01L25/16 , H01L23/49575 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe for multi-chip package (MCP) including a die pad and a plurality of leads. A dielectric layer is formed on the lower surface of the die pad, so that the die pad is etched to form an interconnecting conductor with a bonding region. An insulation layer is formed on the interconnecting conductor and exposes the bonding region, so that a chip or a passive component can be electrically connected to the leads via the interconnecting conductor.
摘要翻译：一种用于包括管芯焊盘和多个引线的多芯片封装（MCP）的引线框架。在芯片焊盘的下表面上形成介质层，从而蚀刻芯片焊盘以形成具有接合区域的互连导体。在互连导体上形成绝缘层并露出接合区域，使得芯片或无源部件能够经由互连导体电连接到引线。

8. 发明授权

US08968595B2 Methods for recycling liquid crystal and forming reformulated liquid crystal mixtures 有权
标题翻译：回收液晶并形成重新配制的液晶混合物的方法
公开(公告)号：US08968595B2
公开(公告)日：2015-03-03
申请号：US13225102
申请日：2011-09-02
申请人： Chien-Wei Lu , Huan-Yi Hung , Tsung-Chou Hsu , Chia-Lin Tsai , Yao-Ting Huang , Meng-Yuh Chen
发明人： Chien-Wei Lu , Huan-Yi Hung , Tsung-Chou Hsu , Chia-Lin Tsai , Yao-Ting Huang , Meng-Yuh Chen
IPC分类号： C09K19/02 , C09K19/04 , B01D11/04 , C09K19/00
CPC分类号： B01D11/0492 , C09K19/00
摘要： Provided are methods for recycling liquid crystal comprising: receiving at least one liquid crystal mixture; and forming a reformulated liquid crystal mixture using at least one portion of the at least one liquid crystal mixture. Also provided are reformulated liquid crystal mixtures comprising at least one recycled liquid crystal mixture and liquid crystals displays devices having one or more reformulated liquid crystal mixtures.
摘要翻译：提供了用于回收液晶的方法，包括：接收至少一种液晶混合物; 以及使用所述至少一种液晶混合物的至少一部分形成重新配制的液晶混合物。还提供了包含至少一种再循环液晶混合物的重新配置的液晶混合物和具有一种或多种重新配制的液晶混合物的液晶显示装置。

9. 发明授权

US07748111B2 Manufacturing process of a carrier 有权
标题翻译：承运人的制造过程
公开(公告)号：US07748111B2
公开(公告)日：2010-07-06
申请号：US11874069
申请日：2007-10-17
申请人： Chien-Hao Wang , Kuo-Hsiang Lin , Yao-Ting Huang
发明人： Chien-Hao Wang , Kuo-Hsiang Lin , Yao-Ting Huang
IPC分类号： H05K3/36 , H05K1/02
CPC分类号： H05K1/183 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/3121 , H01L23/49822 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19105 , H05K3/28 , H05K3/3452 , H05K3/429 , H05K3/4652 , H05K3/4697 , H05K2201/09072 , H05K2201/0959 , H05K2201/0989 , H05K2201/10636 , H05K2201/10674 , H05K2203/049 , H05K2203/063 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A manufacturing process of a carrier is disclosed. First, a first substrate is provided. A circuit layer having a number of contacts is formed on a surface of the first substrate. Then, a solder mask is formed on the circuit layer and exposes the contacts. Next, a second substrate having an opening is bonded to the surface of the first substrate to form a carrier, and the opening exposes the solder mask and the contacts of the first substrate. Since the contacts are located within the opening, a circuit layout space can be increased, and a chip disposed in the opening can be electrically connected to the contacts directly, so as to reduce the thickness of a chip package structure. Besides, the carrier is formed by laminating the first and the second substrates. Hence, the manufacturing process of the carrier is simplified and yield of the carrier is promoted.
摘要翻译：公开了载体的制造方法。首先，提供第一基板。具有多个触点的电路层形成在第一基板的表面上。然后，在电路层上形成焊接掩模，并露出触点。接下来，具有开口的第二基板被接合到第一基板的表面以形成载体，并且该开口使焊料掩模和第一基板的触点暴露。由于触点位于开口内，因此可以增加电路布局空间，并且设置在开口中的芯片可以直接电连接到触点，以便减小芯片封装结构的厚度。此外，通过层叠第一和第二基板形成载体。因此，简化了载体的制造过程，促进了载体的产率。

10. 发明授权

US07575957B2 Leadless semiconductor package and method for manufacturing the same 有权
标题翻译：无铅半导体封装及其制造方法
公开(公告)号：US07575957B2
公开(公告)日：2009-08-18
申请号：US11143676
申请日：2005-06-03
申请人： Yao-Ting Huang , Chih-Te Lin
发明人： Yao-Ting Huang , Chih-Te Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/4846 , H01L21/4828 , H01L23/3121 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49575 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/50 , H01L2224/05554 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the conventional tie bars. The semiconductor chip is disposed on the chip pad and electrically connected to the inner leads. Moreover, the molding compound is formed on the inner leads and the non-conductive ink for encapsulating the semiconductor chip. The non-conductive ink prevents the exposed bottom surfaces of the inner leads from contamination by the molding compound without attaching an external tape during molding. Also the inner leads can be in a multi-row arrangement and the chip pad can be disposed in an optional location.
摘要翻译：无引线半导体封装主要包括多个内引线，芯片焊盘，半导体芯片和模塑料。在每两个内引线之间填充非导电油墨，并且将内引线连接到芯片垫以便替代传统的连接杆。半导体芯片设置在芯片焊盘上并电连接到内引线。此外，在内引线和用于封装半导体芯片的非导电油墨上形成模塑料。非导电油墨防止内部引线的暴露的底部表面被模塑料污染，而不会在模制过程中附着外部胶带。内引线也可以是多列布置，并且芯片焊盘可以设置在可选的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式