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1. 发明申请

US20120018804A1 Guard Ring Integrated LDMOS 有权
标题翻译：保护环集成LDMOS
公开(公告)号：US20120018804A1
公开(公告)日：2012-01-26
申请号：US12842660
申请日：2010-07-23
申请人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
发明人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1083 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/66681 , H01L29/7816 , H01L29/7817
摘要： An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).
摘要翻译：提供了一种LDMOSFET晶体管（100），其包括衬底（101），其中形成有漏极区（116）的外延漂移区（104），源区（112）为其中的第一阱区形成邻近源区（112）形成第一沟道区（14）的栅电极（120），以及接地衬底注入抑制保护结构，其包括与隔离欧姆接触的图案化掩埋层（102）阱区域（103）形成在衬底的预定上部区域中，以与第一阱区域（107）和漏极区域（116）间隔开，其中掩埋层（102）设置在第一阱区域（107），但不在漏极区域（116）的下方。

2. 发明授权

US08278710B2 Guard ring integrated LDMOS 有权
标题翻译：保护环集成LDMOS
公开(公告)号：US08278710B2
公开(公告)日：2012-10-02
申请号：US12842660
申请日：2010-07-23
申请人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
发明人： Vishnu K. Khemka , Stephen J. Cosentino , Tahir A. Khan , Adolfo C. Reyes , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L29/1083 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/66681 , H01L29/7816 , H01L29/7817
摘要： An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).
摘要翻译：提供了一种LDMOSFET晶体管（100），其包括衬底（101），其中形成有漏极区（116）的外延漂移区（104），源区（112）为其中的第一阱区形成邻近源区（112）形成第一沟道区（14）的栅电极（120），以及接地衬底注入抑制保护结构，其包括与隔离欧姆接触的图案化掩埋层（102）阱区域（103）形成在衬底的预定上部区域中，以与第一阱区域（107）和漏极区域（116）间隔开，其中掩埋层（102）设置在第一阱区域（107），但不在漏极区域（116）的下方。

3. 发明授权

US4983531A Method of fabricating a single polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors 失效
标题翻译：制造与制造CMOS晶体管的方法兼容的单个多晶硅双极晶体管的方法
公开(公告)号：US4983531A
公开(公告)日：1991-01-08
申请号：US478390
申请日：1990-02-12
申请人： Stephen J. Cosentino
发明人： Stephen J. Cosentino
IPC分类号： H01L21/285 , H01L21/331 , H01L21/60 , H01L21/8249
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/8249 , H01L29/66272 , Y10S148/019 , Y10S148/123
摘要： An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer over a thin silicon dioxide layer combined with a polysilicon layer. This bipolar structure has a self-aligned, P-type extrinsic base which results in lower base resistance and improved performance.
摘要翻译：通过在与多晶硅层结合的薄二氧化硅层上利用氮化物层来制造BiCMOS集成电路的改进的双极晶体管。该双极结构具有自对准的P型外部碱，导致较低的耐碱性和改进的性能。

4. 发明授权

US4808555A Multiple step formation of conductive material layers 失效
标题翻译：导电材料层的多步形成
公开(公告)号：US4808555A
公开(公告)日：1989-02-28
申请号：US884113
申请日：1986-07-10
申请人： Richard W. Mauntel , Stephen J. Cosentino , Louis C. Parrillo , Patrick J. Holly
发明人： Richard W. Mauntel , Stephen J. Cosentino , Louis C. Parrillo , Patrick J. Holly
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/66575
摘要： A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.
摘要翻译：一种通过从多个导电材料薄层形成导电材料层，至少在两个步骤中形成导电材料层的工艺。导电材料层的两步形成方法的使用允许在形成导电材料的薄层之间的植入步骤和图案化步骤中的工艺通用性。从介电层形成到导电材料层形成步骤的直接转移，以及执行与薄导电层形成相同的设备中的中间工艺步骤有助于薄层彼此粘附以形成总导电材料层。使用原位掺杂的半导体材料，例如原位掺杂的多晶硅和原位掺杂的非晶硅，可以降低可能存在于高于900℃的热循环的其他掺杂剂的暴露，导致这些掺杂剂不期望地迁移。

5. 发明授权

US4745086A Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation 失效
标题翻译：用于轻掺杂漏极形成的可拆卸侧壁间隔，使用一个掩模级和差示氧化
公开(公告)号：US4745086A
公开(公告)日：1988-05-17
申请号：US47589
申请日：1987-05-11
申请人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
发明人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/78 , H01L21/26 , H01L21/265 , H01L21/22
CPC分类号： H01L29/6653 , H01L21/0337 , H01L21/823864 , H01L29/0847 , H01L29/78 , Y10S148/082 , Y10S148/106 , Y10S148/116 , Y10S257/90
摘要： A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.
摘要翻译：一种使用可移除的侧壁间隔物的方法，以最小化在形成CMOS集成电路时形成轻掺杂的漏极（LDD）中的掩模电平的需要。铝或化学气相沉积（CVD）金属如钨是合适的材料，用于在重掺杂的源极/漏极区域注入期间形成存在于CMOS栅极周围的可移除的侧壁间隔物。诸如CVD多晶硅的其它材料也可用于侧壁间隔物。在栅极周围的轻掺杂漏极区域注入之前去除侧壁间隔物。这种植入序列正好与当前对轻掺杂漏极形成实践相反。本发明还包括使用差示氧化物层。第二组一次性侧壁间隔件或永久侧壁间隔件的使用形成可选实施例。

6. 发明授权

US4717683A CMOS process 失效
标题翻译： CMOS工艺
公开(公告)号：US4717683A
公开(公告)日：1988-01-05
申请号：US910927
申请日：1986-09-23
申请人： Louis C. Parrillo , Stephen J. Cosentino , Bridgette A. Bergami
发明人： Louis C. Parrillo , Stephen J. Cosentino , Bridgette A. Bergami
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092 , H01L21/22 , H01L21/265
CPC分类号： H01L21/823807 , H01L21/76218 , H01L27/0928
摘要： A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask. A first N-type implant is performed at energy sufficient to penetrate through the first mask but insufficient to penetrate through the fourth mask. This implant provides punch through protection for P channel transistors to be formed later. A second N-type impurity is implanted into the surface at an implant energy insufficient to penetrate through the first mask to provided field doping. The silicon substrate is then oxidized to form a field oxide at portions of the first and second surface regions which are not covered by the first and second masks.
摘要翻译：公开了一种制造互补绝缘栅场效应晶体管的方法，其包括掺杂场隔离区和可选的穿通保护。在本发明的一个实施例中，提供了具有N型和P型表面区域的硅衬底。形成覆盖两个表面区域的有效区域的第一和第二掩模。然后形成覆盖第一区域和第一掩模的第三掩模。 P型杂质以足以穿透第二掩模但不能透过第三掩模的注入能量注入第二区域。以不足以穿过任一掩模的植入能量来执行第二P型植入物。第一种植入物将有助于防止穿透，而第二种植入物则会涂覆场区域。然后形成覆盖第二区域和第二掩模的第四掩模。以足以穿透第一掩模但不足以穿透第四掩模的能量进行第一N型植入物。该种植体为稍后形成的P沟道晶体管提供穿通保护。以不足以穿透第一掩模的注入能量将第二N型杂质注入表面，以提供场掺杂。然后在不被第一和第二掩模覆盖的第一表面区域和第二表面区域的部分处，氧化硅衬底以形成场氧化物。

7. 发明授权

US5225365A Method of making a substantially planar semiconductor surface 失效
标题翻译：制造基本平面的半导体表面的方法
公开(公告)号：US5225365A
公开(公告)日：1993-07-06
申请号：US860374
申请日：1992-03-30
申请人： Stephen J. Cosentino
发明人： Stephen J. Cosentino
IPC分类号： H01L21/027 , H01L21/266 , H01L21/8238 , H01L21/8249 , H01L27/092
CPC分类号： H01L21/0274 , H01L21/266 , H01L21/823892 , H01L21/8249 , H01L27/0928 , Y10S148/009 , Y10S148/116
摘要： A substantially planar semiconductor surface is formed for fabricating submicron BiCMOS integrated circuits. A lightly doped epitaxial layer is formed on a semiconductor substrate having buried layers formed therein. The substantially planar semiconductor surface is formed by forming a p-type well in the lightly doped epitaxial layer before the step of forming an n-type well in the lightly doped epitaxial layer.
摘要翻译：形成基本上平面的半导体表面用于制造亚微米BiCMOS集成电路。在其中形成有掩埋层的半导体衬底上形成轻掺杂的外延层。通过在轻掺杂的外延层中形成n型阱的步骤之前，在轻掺杂的外延层中形成p型阱来形成基本平坦的半导体表面。

8. 发明授权

US4722909A Removable sidewall spacer for lightly doped drain formation using two mask levels 失效
标题翻译：使用两个掩模级别的轻掺杂漏极形成的可拆卸侧壁间隔件
公开(公告)号：US4722909A
公开(公告)日：1988-02-02
申请号：US780534
申请日：1985-09-26
申请人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
发明人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
IPC分类号： H01L21/033 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/302 , H01L21/312
CPC分类号： H01L29/6653 , H01L21/0337 , H01L21/823864
摘要： A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.
摘要翻译：一种使用可移除的侧壁间隔物的方法，以最小化在形成CMOS集成电路时形成轻掺杂的漏极（LDDS）中的掩模电平的需要。铝或化学气相沉积（CVD）金属如钨是合适的材料，用于在重掺杂的源极/漏极区域注入期间形成存在于CMOS栅极周围的可移除的侧壁间隔物。也可以采用保形材料如CVD多晶硅用于此目的。在栅极周围的轻掺杂漏极区域注入之前去除侧壁间隔物。这种植入顺序与目前为轻掺杂的漏极形成实践相反。

9. 发明授权

US5037768A Method of fabricating a double polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors 失效
标题翻译：制造与制造CMOS晶体管的方法兼容的双重多晶硅双极晶体管的方法
公开(公告)号：US5037768A
公开(公告)日：1991-08-06
申请号：US478896
申请日：1990-02-12
申请人： Stephen J. Cosentino
发明人： Stephen J. Cosentino
IPC分类号： H01L21/285 , H01L21/331
CPC分类号： H01L29/6628 , H01L21/28525 , H01L29/66272
摘要： An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer combined with two polysilicon layers to form a self-aligned P-type extrinsic base which results in lower base resistance and lower base-collector capacitance, and thus improved performance.
摘要翻译：通过利用与两个多晶硅层结合的氮化物层来形成BiCMOS集成电路的改进的双极晶体管，以形成自对准P型外部基极，这导致较低的基极电阻和较低的基极 - 集电极电容，从而提高了性能。

10. 发明授权

US4701775A Buried n.sup.- channel implant for NMOS transistors 失效
标题翻译：埋入n沟道注入用于NMOS晶体管
公开(公告)号：US4701775A
公开(公告)日：1987-10-20
申请号：US789673
申请日：1985-10-21
申请人： Stephen J. Cosentino , James M. Rugg , Richard W. Mauntel
发明人： Stephen J. Cosentino , James M. Rugg , Richard W. Mauntel
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L27/02
CPC分类号： H01L29/1033 , H01L21/2652 , H01L21/823807 , H01L29/1079 , H01L29/1083
摘要： A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.
摘要翻译： MOS集成电路中的n沟道和p沟道器件之下的深埋N沟道覆盖层，无论是互补MOS（CMOS）还是互补MOS（CMOS）。已知使用深的，轻掺杂的n沟道注入来改善p沟道（PMOS）器件的特性，尽管本领域技术人员将期望这种n-注入对n沟道（NMOS）的影响是不利的，设备。已经发现，这样的植入物不仅不会降低NMOS器件，而且实际上改善了它们对于身体效应和结电容的性能。

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