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1. 发明授权

US4701775A Buried n.sup.- channel implant for NMOS transistors 失效
标题翻译：埋入n沟道注入用于NMOS晶体管
公开(公告)号：US4701775A
公开(公告)日：1987-10-20
申请号：US789673
申请日：1985-10-21
申请人： Stephen J. Cosentino , James M. Rugg , Richard W. Mauntel
发明人： Stephen J. Cosentino , James M. Rugg , Richard W. Mauntel
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L27/02
CPC分类号： H01L29/1033 , H01L21/2652 , H01L21/823807 , H01L29/1079 , H01L29/1083
摘要： A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.
摘要翻译： MOS集成电路中的n沟道和p沟道器件之下的深埋N沟道覆盖层，无论是互补MOS（CMOS）还是互补MOS（CMOS）。已知使用深的，轻掺杂的n沟道注入来改善p沟道（PMOS）器件的特性，尽管本领域技术人员将期望这种n-注入对n沟道（NMOS）的影响是不利的，设备。已经发现，这样的植入物不仅不会降低NMOS器件，而且实际上改善了它们对于身体效应和结电容的性能。

2. 发明授权

US4808555A Multiple step formation of conductive material layers 失效
标题翻译：导电材料层的多步形成
公开(公告)号：US4808555A
公开(公告)日：1989-02-28
申请号：US884113
申请日：1986-07-10
申请人： Richard W. Mauntel , Stephen J. Cosentino , Louis C. Parrillo , Patrick J. Holly
发明人： Richard W. Mauntel , Stephen J. Cosentino , Louis C. Parrillo , Patrick J. Holly
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/66575
摘要： A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.
摘要翻译：一种通过从多个导电材料薄层形成导电材料层，至少在两个步骤中形成导电材料层的工艺。导电材料层的两步形成方法的使用允许在形成导电材料的薄层之间的植入步骤和图案化步骤中的工艺通用性。从介电层形成到导电材料层形成步骤的直接转移，以及执行与薄导电层形成相同的设备中的中间工艺步骤有助于薄层彼此粘附以形成总导电材料层。使用原位掺杂的半导体材料，例如原位掺杂的多晶硅和原位掺杂的非晶硅，可以降低可能存在于高于900℃的热循环的其他掺杂剂的暴露，导致这些掺杂剂不期望地迁移。

3. 发明授权

US4722909A Removable sidewall spacer for lightly doped drain formation using two mask levels 失效
标题翻译：使用两个掩模级别的轻掺杂漏极形成的可拆卸侧壁间隔件
公开(公告)号：US4722909A
公开(公告)日：1988-02-02
申请号：US780534
申请日：1985-09-26
申请人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
发明人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
IPC分类号： H01L21/033 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/302 , H01L21/312
CPC分类号： H01L29/6653 , H01L21/0337 , H01L21/823864
摘要： A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.
摘要翻译：一种使用可移除的侧壁间隔物的方法，以最小化在形成CMOS集成电路时形成轻掺杂的漏极（LDDS）中的掩模电平的需要。铝或化学气相沉积（CVD）金属如钨是合适的材料，用于在重掺杂的源极/漏极区域注入期间形成存在于CMOS栅极周围的可移除的侧壁间隔物。也可以采用保形材料如CVD多晶硅用于此目的。在栅极周围的轻掺杂漏极区域注入之前去除侧壁间隔物。这种植入顺序与目前为轻掺杂的漏极形成实践相反。

4. 发明授权

US06461925B1 Method of manufacturing a heterojunction BiCMOS integrated circuit 有权
标题翻译：异质结BiCMOS集成电路的制造方法
公开(公告)号：US06461925B1
公开(公告)日：2002-10-08
申请号：US09539130
申请日：2000-03-30
申请人： Jay P. John , James A. Kirchgessner , Ik-Sung Lim , Michael H. Kaneshiro , Vida Ilderem Burger , Phillip W. Dahl , David L. Stolfa , Richard W. Mauntel , John W. Steele
发明人： Jay P. John , James A. Kirchgessner , Ik-Sung Lim , Michael H. Kaneshiro , Vida Ilderem Burger , Phillip W. Dahl , David L. Stolfa , Richard W. Mauntel , John W. Steele
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A method of manufacturing a heterojunction BiCMOS IC. (100) includes forming a gate electrode (121, 131), forming a protective layer (901, 902) over the gate electrode, forming a semiconductor layer (1101) over the protective layer, depositing an electrically insulative layer (1102, 1103) over the semiconductor layer, using a mask layer (1104) to define a doped region (225) in the semiconductor layer and to define a hole (1201) in the electrically insulative layer, forming an electrically conductive layer (1301) over the electrically insulative layer, using another mask layer (1302) to define an emitter region (240) in the electrically conductive layer and to define an intrinsic base region (231) and a portion of an extrinsic base region (232) in the electrically conductive layer, and using yet another mask layer (1502) to define another portion of the extrinsic base region in the electrically conductive layer.
摘要翻译：一种制造异质结BiCMOS IC的方法。（100）包括形成栅电极（121,131），在所述栅电极上形成保护层（901,902），在所述保护层上形成半导体层（1101），沉积电绝缘层（1102,1103）在所述半导体层之上，使用掩模层（1104）在所述半导体层中限定掺杂区域（225）并且在所述电绝缘层中限定孔（1201），在所述电绝缘层上形成导电层（1301）层，使用另一个掩模层（1302）在导电层中限定发射极区（240）并且在导电层中限定本征基极区（231）和非本征基极区（232）的一部分，以及使用另一个掩模层（1502）来限定导电层中的外部基极区域的另一部分。

5. 发明授权

US5208168A Semiconductor device having punch-through protected buried contacts and method for making the same 失效
标题翻译：具有穿孔保护的接头的半导体器件及其制造方法
公开(公告)号：US5208168A
公开(公告)日：1993-05-04
申请号：US617727
申请日：1990-11-26
申请人： Louis C. Parrillo , Neil B. Henis , Richard W. Mauntel
发明人： Louis C. Parrillo , Neil B. Henis , Richard W. Mauntel
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L21/768 , H01L23/522 , H01L27/08 , H01L29/36 , H01L29/78
CPC分类号： H01L29/36 , H01L21/743 , Y10S148/019 , Y10S148/02
摘要： Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.

6. 发明授权

US5021849A Compact SRAM cell with polycrystalline silicon diode load 失效
标题翻译：具有多晶硅二极管负载的紧凑型SRAM单元
公开(公告)号：US5021849A
公开(公告)日：1991-06-04
申请号：US428570
申请日：1989-10-30
申请人： John R. Pfiester , Richard W. Mauntel
发明人： John R. Pfiester , Richard W. Mauntel
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/861
CPC分类号： G11C11/412 , H01L27/11 , Y10S257/903
摘要： A compact SRAM cell and method for its fabrication are disclosed. The small size of the SRAM cell is achieved by fabricating a diode load immediately above the gate electrode of each of the cross coupled transistors of the cell. In accordance with one embodiment, the gate electrode and diode structure include, in sequence, an N-type doped polycrystalline silicon layer, an electrically conductive diffusion barrier layer, a P-type doped polycrystalline silicon layer and an N-type doped polycrystalline layer.
摘要翻译：公开了一种紧凑的SRAM单元及其制造方法。通过在电池的每个交叉耦合晶体管的栅电极的正上方制造二极管负载来实现SRAM单元的小尺寸。根据一个实施例，栅电极和二极管结构依次包括N型掺杂多晶硅层，导电扩散阻挡层，P型掺杂多晶硅层和N型掺杂多晶层。

7. 发明授权

US4808543A Well Extensions for trench devices 失效
标题翻译：沟槽设备的扩展
公开(公告)号：US4808543A
公开(公告)日：1989-02-28
申请号：US860734
申请日：1986-05-07
申请人： Louis C. Parrillo , Richard W. Mauntel , John M. Barden
发明人： Louis C. Parrillo , Richard W. Mauntel , John M. Barden
IPC分类号： H01L21/225 , H01L21/266 , H01L21/334 , H01L29/94 , H01L29/92
CPC分类号： H01L29/66181 , H01L21/2253 , H01L21/266 , H01L29/945
摘要： A bulge well structure for trench devices in wells of a conductivity type opposite to that of the substrate where the bottom of the trench has localized, extra doping. The additional doping into the bottom of the trench prior to device formation may be implanted while the photoresist mask for the trench formation is still in place. In one embodiment of the method, the trenches and the bulge or well extension formations at their bottoms are created before isolation regions are formed. The structure and method permit increased doping only where needed and are compatible with thin epitaxial layers and sharp transition interfaces of epitaxy with substrate for optimum latchup protection. No extra masks are required and the tight packing allowed by trench technology is not altered. Protection against soft errors and junction leakage by forming DRAM trench capacitors in a well of opposite conductivity type from the substrate may be provided.
摘要翻译：具有导电类型的阱中的沟槽器件的凸起阱结构，其与衬底的底部相反，其中沟槽的底部具有局部化，额外的掺杂。在器件形成之前在沟槽底部的额外掺杂可以被注入，而用于沟槽形成的光致抗蚀剂掩模仍然在位。在该方法的一个实施方案中，在形成隔离区之前，在其底部产生沟槽和凸起或阱延伸构造。该结构和方法允许仅在需要时增加掺杂，并且与薄的外延层和外延与衬底的尖锐过渡界面相适应以实现最佳的闭锁保护。不需要额外的掩模，沟槽技术允许的紧密包装不会改变。可以提供通过在与衬底相反的导电类型的阱中形成DRAM沟槽电容器来防止软错误和结漏电的保护。

8. 发明授权

US4745086A Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation 失效
标题翻译：用于轻掺杂漏极形成的可拆卸侧壁间隔，使用一个掩模级和差示氧化
公开(公告)号：US4745086A
公开(公告)日：1988-05-17
申请号：US47589
申请日：1987-05-11
申请人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
发明人： Louis C. Parrillo , Stephen J. Cosentino , Richard W. Mauntel
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/78 , H01L21/26 , H01L21/265 , H01L21/22
CPC分类号： H01L29/6653 , H01L21/0337 , H01L21/823864 , H01L29/0847 , H01L29/78 , Y10S148/082 , Y10S148/106 , Y10S148/116 , Y10S257/90
摘要： A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.
摘要翻译：一种使用可移除的侧壁间隔物的方法，以最小化在形成CMOS集成电路时形成轻掺杂的漏极（LDD）中的掩模电平的需要。铝或化学气相沉积（CVD）金属如钨是合适的材料，用于在重掺杂的源极/漏极区域注入期间形成存在于CMOS栅极周围的可移除的侧壁间隔物。诸如CVD多晶硅的其它材料也可用于侧壁间隔物。在栅极周围的轻掺杂漏极区域注入之前去除侧壁间隔物。这种植入序列正好与当前对轻掺杂漏极形成实践相反。本发明还包括使用差示氧化物层。第二组一次性侧壁间隔件或永久侧壁间隔件的使用形成可选实施例。

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