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1. 发明授权

US08675385B2 Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权
标题翻译：具有存储单元的半导体器件，写入或从存储器单元读取的方法以及半导体器件制造方法
公开(公告)号：US08675385B2
公开(公告)日：2014-03-18
申请号：US13067773
申请日：2011-06-24
申请人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
发明人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
IPC分类号： G11C17/08
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
摘要翻译：第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。第二电极耦合到第一电极。控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到一个字线。第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。

2. 发明授权

US08530949B2 Semiconductor device with common contact coupling gate wiring integrated with gate electrode of antifuse to diffusion layer 失效
标题翻译：具有公共接触耦合栅极布线的半导体器件与反熔丝扩散层的栅电极集成
公开(公告)号：US08530949B2
公开(公告)日：2013-09-10
申请号：US13250516
申请日：2011-09-30
申请人： Takuji Onuma , Kenichi Hidaka , Hiromichi Takaoka , Yoshitaka Kubota , Hiroshi Tsuda , Kiyokazu Ishige
发明人： Takuji Onuma , Kenichi Hidaka , Hiromichi Takaoka , Yoshitaka Kubota , Hiroshi Tsuda , Kiyokazu Ishige
IPC分类号： H01L29/76 , H01L29/78
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.
摘要翻译：即使利用确定电极中是否有电荷的方法，内部书面信息也无法分析的反熔丝。反熔丝包括栅极绝缘膜，栅电极和第一扩散层。第二扩散层通过器件隔离膜从第一扩散层隔离，并且是与第一扩散层相同的导电类型。栅极布线形成为与栅极电极一体化的部件，并且在器件隔离膜上延伸。常见的接触将栅极布线耦合到第二扩散层。栅电极由掺杂有与第一扩散层相同导电类型的杂质的多晶硅等半导体材料构成。第二扩散层仅耦合到公共接触。

3. 发明申请

US20120044741A1 Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权
标题翻译：具有存储单元的半导体器件，写入或从存储单元读取的方法以及半导体器件制造方法
公开(公告)号：US20120044741A1
公开(公告)日：2012-02-23
申请号：US13067773
申请日：2011-06-24
申请人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
发明人： Hiromichi Takaoka , Kenichi Hidaka , Hiroshi Tsuda , Kiyokazu Ishige , Yoshitaka Kubota , Takuji Onuma
IPC分类号： G11C17/08 , H01L21/336 , H01L27/088
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
摘要翻译：第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。第二电极耦合到第一电极。控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到一个字线。第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。

4. 发明授权

US08982648B2 Semiconductor memory device and antifuse programming method 有权
标题翻译：半导体存储器件和反熔丝编程方法
公开(公告)号：US08982648B2
公开(公告)日：2015-03-17
申请号：US13193186
申请日：2011-07-28
申请人： Takuji Onuma , Kenichi Hidaka , Hiromichi Takaoka , Yoshitaka Kubota , Hiroshi Tsuda
发明人： Takuji Onuma , Kenichi Hidaka , Hiromichi Takaoka , Yoshitaka Kubota , Hiroshi Tsuda
IPC分类号： G11C7/00 , G11C17/18
CPC分类号： G11C17/18
摘要： An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.
摘要翻译：由NMOS晶体管或NMOS电容器构成的反熔丝包括耦合到栅电极的第一端子，耦合到扩散层的第二端子和介于栅极电极和扩散层之间的栅极绝缘膜。编程电路包括具有第一电流驱动能力并执行第一编程操作的第一编程电路和具有大于第一电流驱动能力的第二电流驱动能力的第二编程电路，并且执行第二编程操作以跟随第一编程操作。在第一编程操作中，第一编程电路通过在第一端子和第二端子之间施加第一编程电压来分解栅极绝缘膜。在第二编程操作中，第二编程电路在第一端子和第二端子之间施加低于第一编程电压的第二编程电压。

5. 发明授权

US08519508B2 Semiconductor device having an anti-fuse element and a transistor with a pocket region 有权
标题翻译：具有抗熔丝元件的半导体器件和具有口袋区域的晶体管
公开(公告)号：US08519508B2
公开(公告)日：2013-08-27
申请号：US12938662
申请日：2010-11-03
申请人： Yoshitaka Kubota , Hiroshi Tsuda , Kenichi Hidaka , Takuji Onuma , Hiromichi Takaoka
发明人： Yoshitaka Kubota , Hiroshi Tsuda , Kenichi Hidaka , Takuji Onuma , Hiromichi Takaoka
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.
摘要翻译：半导体器件具有常规的NMOS晶体管和用作反熔丝元件并具有n型沟道区的NMOS晶体管。传统的NMOS晶体管配备有n型延伸区域和p型袋区域，而反熔丝元件没有配备延伸区域和口袋区域。这使得可以提高晶体管的性能，同时提高其栅极电介质膜击穿之后的抗熔丝元件的特性。

6. 发明授权

US08942023B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08942023B2
公开(公告)日：2015-01-27
申请号：US13566575
申请日：2012-08-03
申请人： Hiroshi Tsuda , Yoshitaka Kubota , Kenichi Hidaka , Hiromichi Takaoka
发明人： Hiroshi Tsuda , Yoshitaka Kubota , Kenichi Hidaka , Hiromichi Takaoka
IPC分类号： G11C11/00 , G11C7/24 , G11C13/00 , G06F21/75 , G06F21/79
CPC分类号： G11C7/24 , G06F21/75 , G06F21/79 , G11C13/0004 , G11C13/003 , G11C13/0059 , G11C17/16 , G11C2213/74 , G11C2213/79 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.
摘要翻译：提供了一种使用电阻随机存取存储器（ReRAM）元件并具有改进的防篡改性的半导体器件。半导体器件设置有存储一位单元数据的单元单元和控制电路。单位单元包括n个ReRAM元素（n是2或更大的整数）。 ReRAM元素中的至少一个是记录单元数据的有效元素。在读取单元数据时，控制电路至少选择有效元件并将其上记录的数据读取为单元数据。

7. 发明申请

US20110122672A1 Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110122672A1
公开(公告)日：2011-05-26
申请号：US12931159
申请日：2011-01-26
申请人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
发明人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
IPC分类号： G11C17/16 , H01L27/105
CPC分类号： H01L27/112 , G11C17/16 , H01L27/11206
摘要： A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
摘要翻译：一种非易失性半导体存储器件，具有其中工作电位很小并且外围电路的规模减小的存储单元包括在半导体衬底的通道两侧具有源极/漏极的选择晶体管，并具有栅电极通过厚栅绝缘膜设置在通道上; 在与所述选择晶体管相邻的区域中形成在所述半导体衬底上的元件隔离区; 邻近元件隔离区域的反熔丝，其具有形成在半导体衬底上的下电极，并且具有通过薄栅绝缘膜在元件隔离区和下电极之间的区域中设置在半导体衬底上的上电极; 以及电连接源极和上部电极并接触源极和上部电极的连接接点。

8. 发明授权

US08592942B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US08592942B2
公开(公告)日：2013-11-26
申请号：US12320102
申请日：2009-01-16
申请人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
发明人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
IPC分类号： H01L27/11
CPC分类号： H01L27/112 , G11C17/16 , H01L27/11206
摘要： A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

9. 发明申请

US20090184350A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090184350A1
公开(公告)日：2009-07-23
申请号：US12320102
申请日：2009-01-16
申请人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
发明人： Noriaki Kodama , Kenichi Hidaka , Hiroyuki Kobatake , Takuji Onuma
IPC分类号： H01L29/94 , H01L29/66
CPC分类号： H01L27/112 , G11C17/16 , H01L27/11206
摘要： A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
摘要翻译：一种非易失性半导体存储器件，具有其中工作电位很小并且外围电路的规模减小的存储单元包括在半导体衬底的通道两侧具有源极/漏极的选择晶体管，并具有栅电极通过厚栅绝缘膜设置在通道上; 在与所述选择晶体管相邻的区域中形成在所述半导体衬底上的元件隔离区; 邻近元件隔离区域的反熔丝，其具有形成在半导体衬底上的下电极，并且具有通过薄栅绝缘膜在元件隔离区和下电极之间的区域中设置在半导体衬底上的上电极; 以及电连接源极和上部电极并接触源极和上部电极的连接接点。

10. 发明授权

US09105338B2 OTP memory 有权
标题翻译： OTP内存
公开(公告)号：US09105338B2
公开(公告)日：2015-08-11
申请号：US13584899
申请日：2012-08-14
申请人： Kenichi Hidaka , Yoshitaka Kubota
发明人： Kenichi Hidaka , Yoshitaka Kubota
IPC分类号： G11C7/00 , G11C17/16 , G11C17/18 , H01L27/112 , H01L49/02
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L28/40
摘要： The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
摘要翻译：本发明提供了具有较高保密性的OTP存储器。存储单元具有形成第一和第二节点之间的电流路径的存储晶体管，形成第三和第四节点之间的电流路径的选择晶体管，第三节点通过线耦合到存储晶体管的栅极，以及电容器耦合到第一个节点。通过施加不破坏但会使栅极氧化膜劣化并且将栅极漏电流增加到存储晶体管的高电压，写入数据。可以通过存在/不存在在电容器中累积的电荷的泄漏来读取数据。由于不能通过物理分析区分栅极氧化膜的劣化位置，因此机密性高。

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