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1. 发明授权

US6026422A Large-scale multiplication with addition operation method and system 失效
标题翻译：大规模乘法加法运算法和系统
公开(公告)号：US6026422A
公开(公告)日：2000-02-15
申请号：US31889
申请日：1998-02-27
申请人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa
发明人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa
IPC分类号： G06F17/12 , G06F17/10 , G06F17/11
CPC分类号： G06F17/10
摘要： Electron repulsion integrals are classified according to atomic nucleus coordinates, etc., coefficients are generated and are stored in a data memory, multiplication with addition operation is executed according to a product sum procedure of auxiliary integrals of recursive order 1 or less, and the result is stored in the data memory. Next, density matrix element is stored in the data memory, a multiplication with addition operation procedure of an electron repulsion integral of recursive order 2 not containing any procedure of recursive order 1 or less is generated, and an instruction memory is updated. Multiplication with addition operation is executed while data is read from the data memory, and the result is stored in the data memory. At the termination of the product sum procedure, calculation of electron repulsion integral gRstu is complete and the Fock matrix element value is updated. The Fock matrix element containing electron repulsion integral when a linear combination constant to minimize the expected value of molecule energy required for molecular orbital calculation is found is thus found by performing recursive multiplication with addition operation.
摘要翻译：电子排斥积分根据原子核坐标等进行分类，生成系数并存储在数据存储器中，根据递归顺序1或更小的辅助积分的乘积和过程执行与加法运算相乘的乘法运算，结果存储在数据存储器中。接下来，密度矩阵元素被存储在数据存储器中，产生与不包含递归顺序1或更小的任何过程的递归阶数2的电子排斥积分的加法运算过程相乘，并且更新指令存储器。在从数据存储器读取数据的同时执行加法运算的乘法运算，结果存储在数据存储器中。在产品和程序结束时，电子排斥积分gRstu的计算完成，更新了Fock矩阵元素值。因此，通过执行加法运算的递归乘法，可以发现，当发现分子轨道计算所需分子能量的期望值最小化的线性组合常数时，含有电子斥力积分的Fock矩阵元素。

2. 发明授权

US06799151B1 Method and apparatus for parallel processing 失效
标题翻译：并行处理方法和装置
公开(公告)号：US06799151B1
公开(公告)日：2004-09-28
申请号：US09544201
申请日：2000-04-07
申请人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Shigeru Obara
发明人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Shigeru Obara
IPC分类号： G06F1750
CPC分类号： G06F9/5066 , G06F8/45 , G06F17/10
摘要： Matrix element calculation carried out efficiently without the overhead of communication between a host computer and processor elements even in parallel calculation utilizing a low-cost communication device and multiple processor elements having memories of a small capacity. In a method for calculating molecular orbitals, for example, all elements F(I, J) of a Fock matrix are calculated where an outermost loop is a loop associated with combinations (RT) of contracted shell R and contracted shell T which satisfy relationships R≦Nshell and T≦R. A second loop is a loop associated with contracted shell S, and a third loop is a loop associated with contracted shell U. Alternatively, the second loop is a loop associated with the contracted shell U, and the third loop is a loop associated with the contracted shell S. The value of S ranges from 1 to R, and the value of U ranges from 1 to R. Calculation of predetermined electron repulsion integrals and calculation of a predetermined part of Fock matrix elements utilizing the result of the calculation is carried out inside the third loop.
摘要翻译：即使在使用低成本通信装置的并行计算和具有小容量的存储器的多个处理器元件的情况下，也可以有效地进行矩阵元素计算，而无需主计算机和处理器元件之间的通信开销。在用于计算分子轨道的方法中，例如，计算Fock矩阵的所有元素F（I，J），其中最外面的循环是与收缩壳体R和收缩壳体T的组合（RT）相关联的回路，其满足关系R <= Nshell和T <= R。第二个循环是与收缩壳体S相关联的循环，第三个循环是与收缩的壳体U相关联的循环。或者，第二个循环是与收缩的壳体U相关联的循环，第三个循环是与 S的值范围从1到R，U的值在1到R之间。使用计算结果计算预定的电子斥力积分和计算预定部分的Fock矩阵元素在第三个循环内。

3. 发明授权

US06631391B1 Parallel computer system and parallel computing method 失效
标题翻译：并行计算机系统和并行计算方法
公开(公告)号：US06631391B1
公开(公告)日：2003-10-07
申请号：US09544359
申请日：2000-04-06
申请人： Shinjiro Inabata , So Yamada , Nobuaki Miyakawa , Takashi Amisaki , Hajime Takashima , Kunihiro Kitamura
发明人： Shinjiro Inabata , So Yamada , Nobuaki Miyakawa , Takashi Amisaki , Hajime Takashima , Kunihiro Kitamura
IPC分类号： G06F738
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30025 , G06F9/3885
摘要： There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high calculation speed. A system is constructed by connecting a host processor with a plurality of special purpose processors via buses. The host processor carries out the operation in a format of double-precision floating-point and the special purpose processor carries out the operation in an internal format of floating-point. The special purpose processor comprises an input data converting section for converting from the double-precision to the internal format and an output data converting section for converting from the internal format to the double-precision. Because the sign part and the exponent part can use data in common in the data before and after the conversion, only the mantissa part is converted by a specific procedure.
摘要翻译：提供了并行计算机和并行计算方法，其允许执行高精度并行计算，而不需要硬件规模，同时保持高的计算速度。通过总线将主机处理器与多个专用处理器连接构成系统。主机处理器以双精度浮点格式进行操作，专用处理器以浮点的内部格式进行操作。专用处理器包括用于从双精度转换为内部格式的输入数据转换部分和用于从内部格式转换为双精度的输出数据转换部分。因为符号部分和指数部分可以在转换之前和之后的数据中使用共同的数据，所以仅通过特定过程转换尾数部分。

4. 发明授权

US6073155A Floating-point accumulator 失效
标题翻译：浮点累加器
公开(公告)号：US6073155A
公开(公告)日：2000-06-06
申请号：US901671
申请日：1997-07-28
申请人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
发明人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
IPC分类号： G06F7/485 , G06F7/50 , G06F17/10 , G06F7/38
CPC分类号： G06F7/485
摘要： To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.
摘要翻译：为了获得足够精确的浮点积累结果，即使计算量很大，根据本发明的浮点累加器如下构成：当两个浮点数据存储在任何移位寄存器中时，两个数据分别通过连接到缓冲器移位寄存器的一个BUS0和BUS1输出。两个输出数据通过BUS0和BUS1输入加法器，并在添加浮点数后作为相加结果数据输出。上述相加的结果数据通过BUSW和多路复用器返回到移位寄存器的每个输入，并且在相加之前通过移位寄存器保持浮点数据之一来写入与移位寄存器相对应的移位寄存器。通过重复上述操作来累积浮点数。

5. 发明授权

US07370328B2 Method for assigning job in parallel processing method and parallel processing method 失效
标题翻译：并行处理方法和并行处理方法分配作业的方法
公开(公告)号：US07370328B2
公开(公告)日：2008-05-06
申请号：US10257913
申请日：2002-04-25
申请人： Sou Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Unpei Nagashima
发明人： Sou Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Unpei Nagashima
IPC分类号： G06F9/44 , G06F15/16 , G06F15/163
CPC分类号： G06F9/5066 , G06F9/4881
摘要： When parallel processing is executed by parallel computers composed of a host computer and a plurality of processors connected to the host computer through a common bus, there is provided a method of assigning jobs to respective processors with high efficiency. A job in which a ratio between a communication time and a calculation time is larger than a predetermined value or larger than a fraction of processors and a job in which a ratio between a communication time and a calculation time is smaller than a predetermined value or smaller than a fraction of processors can be alternately assigned to respective processors. Alternatively, jobs are assigned to respective processors in such a manner that a plurality of processors and a plurality of jobs are divided into a plurality of groups in a one-to-one relation, jobs in which sizes comprising communication time and calculation time and ratios between the communication times and the calculation times approximate to each other may belong to different job groups and the order in which the jobs in which the sizes comprising the communication time and the calculation time and the ratios between the communication times and the calculation times approximate to each other are assigned within respective job groups may differ from each other among a plurality of job groups.
摘要翻译：当并行处理由主计算机和通过公共总线连接到主计算机的多个处理器组成的并行计算机执行时，提供了一种以高效率将作业分配给各个处理器的方法。其中通信时间和计算时间之间的比率大于预定值或大于处理器的一部分的工作，以及通信时间和计算时间之间的比率小于预定值或更小的作业可以将一小部分处理器交替分配给相应的处理器。或者，将作业分配给各个处理器，使得多个处理器和多个作业以一对一的关系被分成多个组，其中包括通信时间和计算时间和比率的尺寸的作业在通信时间和彼此近似的计算时间之间可以属于不同的作业组，并且其中包括通信时间和计算时间的尺寸以及通信时间与计算时间之间的比率近似于彼此分配在各个作业组中可以在多个作业组中彼此不同。

6. 发明申请

US20100015797A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20100015797A1
公开(公告)日：2010-01-21
申请号：US12063718
申请日：2006-08-25
申请人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
发明人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
IPC分类号： H01L21/768
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L23/585 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/0694 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.
摘要翻译：当将钨膜（43）嵌入形成在晶片（W2）和氧化硅膜（36）上的导电槽（4A）内并具有高纵横比，钨膜的成膜和回蚀（ 43）在相同装置的腔室中连续地进行，因此，在一个成膜步骤中沉积的钨膜（43）的膜厚变薄。由此，避免了钨膜（43）的剥离，微裂纹的产生，以及晶片（W2）的翘曲和裂纹的发生等问题。

7. 发明授权

US5596511A Computing method and apparatus for a many-body problem 失效
标题翻译：多体问题的计算方法和装置
公开(公告)号：US5596511A
公开(公告)日：1997-01-21
申请号：US186029
申请日：1994-01-25
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F19/701
摘要： A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.
摘要翻译：在计算作用于特定颗粒或相关电位的库仑力时，产生包括位于特定颗粒的预定距离内的颗粒数的近端粒子列表。此后，仅基于近端粒子列表中包含的粒子计算作用于特定粒子或相关电位的范德华力。

8. 发明授权

US4665505A Write circuit for use in semiconductor storage device 失效
标题翻译：用于半导体存储设备的写电路
公开(公告)号：US4665505A
公开(公告)日：1987-05-12
申请号：US685552
申请日：1984-12-24
申请人： Nobuaki Miyakawa , Yoshiaki Yazawa , Shoichi Ozeki , Kinya Mitsumoto
发明人： Nobuaki Miyakawa , Yoshiaki Yazawa , Shoichi Ozeki , Kinya Mitsumoto
IPC分类号： G11C11/413 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1096 , G11C7/1078
摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.
摘要翻译：一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。写入电路实现更少的功耗。

9. 发明申请

US20100164055A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER 有权
标题翻译：半导体器件制造方法，半导体器件和晶体管
公开(公告)号：US20100164055A1
公开(公告)日：2010-07-01
申请号：US12718061
申请日：2010-03-05
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L23/48
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由直通隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。随后，将导电膜埋入深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

10. 发明授权

US07705455B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07705455B2
公开(公告)日：2010-04-27
申请号：US12064762
申请日：2006-08-25
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由通过隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。随后，将导电膜埋在深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

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