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    • 1. 发明授权
    • Stacked-fringe integrated circuit capacitors
    • 堆叠边缘集成电路电容器
    • US5978206A
    • 1999-11-02
    • US940847
    • 1997-09-30
    • Ken A. NishimuraScott D. WillinghamWilliam J. McFarland
    • Ken A. NishimuraScott D. WillinghamWilliam J. McFarland
    • H01G4/33H01L21/02H01L21/822H01L23/522H01L27/04H01L27/08H01L29/92H01G4/005H01G4/228
    • H01L27/0805H01L23/5223H01L28/82H01L2924/0002
    • A capacitor that is adapted for construction over a substrate in the metal interconnect layers provided by conventional integrated circuit processes. The capacitor includes a first conducting layer separated from the substrate by a first dielectric layer and a second conducting layer separated from the first conduction layer by a second dielectric layer. The second conducting layer is divided into a plurality of electrically isolated conductors in an ordered array. Every other one of the conductors is connected to a first terminal, and the remaining conductors are connected to a second terminal. The first conducting layer includes at least one conductor which is connected to the first terminal. In one embodiment of the invention, the first conducting layer also includes a plurality of electrically isolated conductors in an ordered array, every other one of the conductors being connected to the first terminal and the remaining conductors being connected the second terminal.
    • 适用于通过常规集成电路工艺提供的金属互连层中的衬底上的结构的电容器。 电容器包括通过第一电介质层与衬底分离的第一导电层和通过第二电介质层与第一导电层分离的第二导电层。 第二导电层被分成多个以有序阵列的电绝缘导体。 导体中的每一根连接到第一端子,其余的导体连接到第二端子。 第一导电层包括连接到第一端子的至少一个导体。 在本发明的一个实施例中,第一导电层还包括有序阵列中的多个电绝缘导体,每个导体中的每一个连接到第一端子,其余的导体与第二端子连接。
    • 2. 发明授权
    • Method for extending the output range of pulse-width based phase
detectors
    • 扩展基于脉冲宽度的相位检测器的输出范围的方法
    • US5952853A
    • 1999-09-14
    • US997148
    • 1997-12-23
    • Scott D. WillinghamWilliam J. McFarland
    • Scott D. WillinghamWilliam J. McFarland
    • G01R25/00H03D13/00H03K5/26H03L7/081H03L7/085H03L7/089
    • G01R25/00H03D13/004H03L7/081H03L7/089
    • A circuit for generating a signal that is proportional to the phase difference between a reference signal and a variable frequency signal. The circuit includes a reference generating circuit for generating N phase shifted reference signals from the reference signal. Each of the phase shifted reference signals has the same frequency and a different phase. The phase of the n.sup.th one of the phase shifted reference signals is equal to 360n/N degrees, where N>1 and n runs from 0 to N-1. A phase detection circuit generates a phase output signal proportional to the phase difference between the variable frequency signal and the phase shifted reference signal currently being outputted by the reference generating circuit. The phase output signal has value of I when the output signal corresponds to a phase difference of 360/N degrees. An overflow detection circuit determines when the phase output signal has an absolute value greater than I and generates a count signal and a phase adjustment signal when this situation is detected. The phase adjustment signal is coupled to the reference generating circuit and causes the reference generating circuit to select a new phase shifted reference signal. A counter is then incremented/decremented to track the accumulated phase adjustments. A digital to analog converter converts the digital value in the counter to a signal having an amplitude equal to MI, where M is the digital value. A sum circuit adds this signal to the phase output signal.
    • 用于产生与参考信号和可变频率信号之间的相位差成比例的信号的电路。 电路包括用于从参考信号产生N个相移参考信号的参考产生电路。 每个相移参考信号具有相同的频率和不同的相位。 第n个相移参考信号的相位等于360n / N度,其中N≥1且n从0到N-1。 相位检测电路产生与参考发生电路当前正在输出的可变频率信号和相移参考信号之间的相位差成比例的相位输出信号。 当输出信号对应于360 / N度的相位差时,相位输出信号的值为I。 溢出检测电路确定相位输出信号何时具有大于I的绝对值,并且当检测到这种情况时产生计数信号和相位调整信号。 相位调整信号耦合到参考产生电路,并使基准产生电路选择新的相移基准信号。 然后计数器递增/递减,以跟踪累积的相位调整。 数模转换器将计数器中的数字值转换为幅度等于MI的信号,其中M是数字值。 总和电路将该信号添加到相位输出信号。