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1. 发明授权

US08013377B2 Method for producing an integrated circuit and arrangement comprising a substrate 有权
标题翻译：一种用于制造集成电路的方法和包括衬底的装置
公开(公告)号：US08013377B2
公开(公告)日：2011-09-06
申请号：US12269612
申请日：2008-11-12
申请人： Peter Baars , Stefan Tegen , Klaus Muemmler
发明人： Peter Baars , Stefan Tegen , Klaus Muemmler
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/90 , H01L27/10852
摘要： Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.
摘要翻译：本发明的实施例涉及一种包括载体的集成电路，其具有具有第一电极和第二电极的电容器。第一电极具有电介质层A层序列布置在载体上，电容器以所述层序列引入，其中层序列具有布置在第一支撑层上方一段距离处的第一支撑层和第二支撑层，其中第一和第二支撑层邻接电容器的第一电极。还提供了制造集成电路的方法。

2. 发明申请

US20100032635A1 ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION 失效
标题翻译：低电阻垂直二极管阵列及其生产方法
公开(公告)号：US20100032635A1
公开(公告)日：2010-02-11
申请号：US12188401
申请日：2008-08-08
申请人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： H01L47/00 , H01L29/66 , H01L21/00
CPC分类号： H01L27/24 , Y10S257/91
摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
摘要翻译：描述了包括存储器单元阵列和相应的制造方法的集成电路。每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

3. 发明授权

US07659602B2 Semiconductor component with MIM capacitor 失效
标题翻译：具有MIM电容器的半导体元件
公开(公告)号：US07659602B2
公开(公告)日：2010-02-09
申请号：US12131728
申请日：2008-06-02
申请人： Stefan Tegen , Klaus Muemmler , Peter Baars , Odo Wunnicke
发明人： Stefan Tegen , Klaus Muemmler , Peter Baars , Odo Wunnicke
IPC分类号： H01L49/00
CPC分类号： H01L28/90 , H01L28/86
摘要： A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.
摘要翻译：描述形成电容器的结构和方法。在一个实施例中，电容器包括圆柱形第一电极，其具有由底表面和内侧壁表面限定的内部部分，第一电极还具有外侧壁，第一电极由导电材料形成。绝缘填充材料设置在第一电极的内部部分内。电容器电介质设置在第一电极的外侧壁的至少一部分附近。第二电极邻近第一电极的外侧壁设置，并由电容器电介质分离。第二电极不形成在第一电极的内部。

4. 发明申请

US20090008694A1 Integrated circuit and corresponding manufacturing method 有权
标题翻译：集成电路及相应的制造方法
公开(公告)号：US20090008694A1
公开(公告)日：2009-01-08
申请号：US11825228
申请日：2007-07-05
申请人： Klaus Muemmler , Peter Baars , Stefan Tegen
发明人： Klaus Muemmler , Peter Baars , Stefan Tegen
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/66666 , H01L27/10876 , H01L27/10894 , H01L29/7827
摘要： The present invention provides an integrated circuit including a field effect transistor formed in an active area segment of a semiconductor substrate, the transistor comprising: a first and a second source/drain contact region; and a channel region arranged in a groove formed in the active area segment and extending to a groove depth larger than a lower first contact depth, wherein the second source/drain contact region is arranged at a vertical extension above the extension of the first source/drain contact region and a corresponding manufacturing method.
摘要翻译：本发明提供一种集成电路，其包括形成在半导体衬底的有源区段中的场效应晶体管，该晶体管包括：第一和第二源极/漏极接触区域; 以及沟槽区域，布置在形成在有源区段中的沟槽中并且延伸到大于下第一接触深度的沟槽深度，其中第二源极/漏极接触区域布置成在第一源极/漏极接触区域的延伸部之上的垂直延伸部处，漏极接触区域和相应的制造方法。

5. 发明申请

US20070037334A1 Memory device and method of manufacturing a memory device 失效
标题翻译：存储器件和制造存储器件的方法
公开(公告)号：US20070037334A1
公开(公告)日：2007-02-15
申请号：US11203927
申请日：2005-08-15
申请人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
发明人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L28/90 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.
摘要翻译：本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。牺牲层在保持在周边部分的同时从阵列部分选择性地移除。这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

6. 发明申请

US20090085084A1 Integrated Circuit and Methods of Manufacturing the Same 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20090085084A1
公开(公告)日：2009-04-02
申请号：US11863528
申请日：2007-09-28
申请人： Stefan Tegen , Klaus Muemmler , Peter Baars , Uta Mierau
发明人： Stefan Tegen , Klaus Muemmler , Peter Baars , Uta Mierau
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L21/0274 , H01L21/31144 , H01L21/32139 , H01L21/76808 , H01L21/76816 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.
摘要翻译：一种制造集成电路的方法包括在衬底的阵列区域中形成着色焊盘，各个着陆焊盘电耦合到形成在阵列区域中的衬底中的各个器件的部分。该方法还包括在衬底的周边区域内形成布线。形成着陆焊盘并形成布线包括在阵列和周边区域均有效的共同光刻工艺。集成电路的布线和着陆焊盘是自对准的。

7. 发明授权

US07482221B2 Memory device and method of manufacturing a memory device 失效
标题翻译：存储器件和制造存储器件的方法
公开(公告)号：US07482221B2
公开(公告)日：2009-01-27
申请号：US11203927
申请日：2005-08-15
申请人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
发明人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.
摘要翻译：本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。牺牲层在保持在周边部分的同时从阵列部分选择性地移除。这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

8. 发明申请

US20070155119A1 Method of manufacturing a field effect transistor device with recessed channel and corner gate device 有权
标题翻译：具有凹槽和角栅装置的场效应晶体管器件的制造方法
公开(公告)号：US20070155119A1
公开(公告)日：2007-07-05
申请号：US11321450
申请日：2005-12-30
申请人： Klaus Muemmler , Peter Baars , Stefan Tegen
发明人： Klaus Muemmler , Peter Baars , Stefan Tegen
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L27/10876 , H01L29/4236 , H01L29/66545 , H01L29/66553
摘要： Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.
摘要翻译：具有拐角栅极器件的凹槽通道阵列晶体管（RCAT）的制造包括在包括栅极沟槽的半导体鳍片之间形成凹穴以及沿着半导体鳍片的长边延伸的相邻浅沟槽隔离件。保护衬套覆盖半导体鳍片和栅极沟槽和凹穴的底部中的沟槽隔离。绝缘体套环形成在门槽和凹穴的暴露的上部中，其中绝缘体环的下边缘对应于形成在半导体鳍内的源/漏区的下边缘。保护衬垫被取下。栅极槽和凹穴的底部被栅极电介质和掩埋栅极导体层覆盖。保护衬垫避免了半导体鳍片的有源区域和绝缘体套环之间的多晶硅残留。

9. 发明授权

US08284596B2 Integrated circuit including an array of diodes coupled to a layer of resistance changing material 失效
标题翻译：集成电路包括耦合到电阻变化材料层的二极管阵列
公开(公告)号：US08284596B2
公开(公告)日：2012-10-09
申请号：US12135439
申请日：2008-06-09
申请人： Igor Kasko , Thomas Happ , Andreas Walter , Stefan Tegen , Peter Baars , Klaus Muemmler
发明人： Igor Kasko , Thomas Happ , Andreas Walter , Stefan Tegen , Peter Baars , Klaus Muemmler
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/16
摘要： An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.
摘要翻译：集成电路包括二极管阵列和耦合到每个二极管的电极。集成电路包括耦合到电极的电阻变化材料层和耦合到电阻变化材料层的位线。电阻变化材料层在每个电极和每个位线的每个交点处提供电阻改变元件。

10. 发明授权

US07804708B2 Integrated circuit including an array of memory cells and method 有权
标题翻译：集成电路包括一组存储单元和方法
公开(公告)号：US07804708B2
公开(公告)日：2010-09-28
申请号：US12182698
申请日：2008-07-30
申请人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： G11C11/00 , G11C5/06 , H01L29/02
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
摘要翻译：一种包括存储单元阵列和方法的集成电路。在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

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