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1. 发明授权

US07482221B2 Memory device and method of manufacturing a memory device 失效
标题翻译：存储器件和制造存储器件的方法
公开(公告)号：US07482221B2
公开(公告)日：2009-01-27
申请号：US11203927
申请日：2005-08-15
申请人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
发明人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.
摘要翻译：本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。牺牲层在保持在周边部分的同时从阵列部分选择性地移除。这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

2. 发明授权

US07566611B2 Manufacturing method for an integrated semiconductor structure 失效
标题翻译：集成半导体结构的制造方法
公开(公告)号：US07566611B2
公开(公告)日：2009-07-28
申请号：US11443652
申请日：2006-05-31
申请人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
发明人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L27/10897
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact hole in said peripheral device region, said at least one other contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one other contact hole with a respective contact plug.
摘要翻译：本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：在存储单元区域中提供具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域和外围设备区域上沉积由碳制成的或由含碳材料制成的第一保护层; 在所述存储单元区域中的所述第一保护层上形成掩模层; 通过在蚀刻步骤中去除所述外围设备区域中的所述第一保护层，在所述外围设备区域中暴露所述至少一个栅极堆叠的所述盖，其中所述掩模层用作所述存储单元区域中的掩模; 从所述存储单元区域去除所述掩模层和所述第一保护层; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔，所述第一接触孔暴露接触区域; 在所述外围设备区域中形成至少另一个接触孔，所述至少一个其它接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或位于所述栅极堆叠中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少一个其它接触孔。

3. 发明授权

US07371657B2 Method for forming an isolating trench with a dielectric material 失效
标题翻译：用介电材料形成隔离沟槽的方法
公开(公告)号：US07371657B2
公开(公告)日：2008-05-13
申请号：US11252878
申请日：2005-10-19
申请人： Uwe Wellhausen , Henry Heidemeyer , Joern Regul
发明人： Uwe Wellhausen , Henry Heidemeyer , Joern Regul
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/10826 , H01L27/10844 , H01L29/785
摘要： The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.
摘要翻译：本发明涉及一种形成具有介电材料的半导体器件的隔离沟槽的方法，以及在存储器件中形成隔离沟槽的方法。

4. 发明申请

US20070281417A1 Manufacturing method for an integrated semiconductor structure 失效
标题翻译：集成半导体结构的制造方法
公开(公告)号：US20070281417A1
公开(公告)日：2007-12-06
申请号：US11443652
申请日：2006-05-31
申请人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
发明人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
IPC分类号： H01L21/8244
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L27/10897
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said said memory cell region; removing said said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact hole in said peripheral device region, said at least one other contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one other contact hole with a respective contact plug.
摘要翻译：本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：在存储单元区域中提供具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域和外围设备区域上沉积由碳制成的或由含碳材料制成的第一保护层; 在所述存储单元区域中的所述第一保护层上形成掩模层; 通过在蚀刻步骤中去除所述外围设备区域中的所述第一保护层，在所述外围设备区域中暴露所述至少一个栅极堆叠的所述盖，其中所述掩模层用作所述存储单元区域中的掩模; 从所述存储单元区域中去除所述掩模层和所述第一保护层; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔，所述第一接触孔暴露接触区域; 在所述外围设备区域中形成至少另一个接触孔，所述至少一个其它接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或位于所述栅极堆叠中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少一个其它接触孔。

5. 发明申请

US20070253233A1 Semiconductor memory device and method of production 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070253233A1
公开(公告)日：2007-11-01
申请号：US11393363
申请日：2006-03-30
申请人： Torsten Mueller , Peter Baars , Klaus Muemmler , Joern Regul , Christian Kapteyn
发明人： Torsten Mueller , Peter Baars , Klaus Muemmler , Joern Regul , Christian Kapteyn
IPC分类号： G11C5/02
CPC分类号： H01L27/115 , G11C5/063 , G11C7/18 , G11C8/14 , H01L27/11568
摘要： A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that a unique addressing of individual memory cells is possible.
摘要翻译：一种器件包括垂直于主衬底表面布置的存储器单元阵列。阵列设有较低位线，字线和高位线。下位线和上位线分别以这样的方式接触连接到下源极/漏极区域和对应的上部源极/漏极区域，使得各个存储器单元的独特寻址是可能的。

6. 发明申请

US20080230839A1 Method of producing a semiconductor structure 审中-公开
标题翻译：半导体结构的制造方法
公开(公告)号：US20080230839A1
公开(公告)日：2008-09-25
申请号：US11728196
申请日：2007-03-23
申请人： Joern Regul , Joerg Radecker , Olaf Storbeck , Kristin Schupke , Tobias Mono
发明人： Joern Regul , Joerg Radecker , Olaf Storbeck , Kristin Schupke , Tobias Mono
IPC分类号： H01L29/76 , H01L21/44 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247 , H01L29/6656
摘要： The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.
摘要翻译：本发明涉及一种制造半导体结构的方法，包括以下步骤：制造栅极叠层结构并氧化至少一部分栅叠层结构的侧壁，其中氧化步骤在低于500℃的温度下进行使用包含氧自由基的工艺气体。

7. 发明申请

US20080124920A1 Fabrication method for an integrated circuit structure 审中-公开
标题翻译：集成电路结构的制造方法
公开(公告)号：US20080124920A1
公开(公告)日：2008-05-29
申请号：US11985067
申请日：2007-11-13
申请人： Clemens Fitz , Axel Buerke , Jens Hahn , Frank Jakubowski , Tobias Mono , Joern Regul , Sven Schmidbauer
发明人： Clemens Fitz , Axel Buerke , Jens Hahn , Frank Jakubowski , Tobias Mono , Joern Regul , Sven Schmidbauer
IPC分类号： H01L21/44
CPC分类号： H01L21/28247 , H01L21/28061 , H01L29/4941
摘要： The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6′, 7′, 8′) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6′) composed of Ti on the polysilicon layer (5); a barrier layer (7′) composed of WN on the contact layer (6′); and a metal layer (8′) composed of W on the barrier layer (7′); wherein steps iii) and iv) are carried out as PVD steps using krypton and/or xenon as sputtering gas; and annealing the layer stack (5, 6′, 7′, 8′) in a thermal step in the temperature range of between 600 and 950° C.
摘要翻译：本发明提供了一种用于集成电路结构的制造方法，包括以下步骤：通过在栅介电层（9）上依次沉积多晶硅层（5）形成电极层堆叠（5,6'，7'，8' ; 在多晶硅层（5）上由Ti构成的接触层（6'）; 在接触层（6'）上由WN组成的阻挡层（7'）; 和由阻挡层（7'）上的W构成的金属层（8'）。其中步骤iii）和iv）作为PVD步骤使用氪和/或氙作为溅射气体进行; 并且在600-950℃的温度范围内的热步骤中退火层堆叠（5,6'，7'，8'）。

8. 发明申请

US20070087516A1 Method for forming an isolating trench with a dielectric material 失效
标题翻译：用介电材料形成隔离沟槽的方法
公开(公告)号：US20070087516A1
公开(公告)日：2007-04-19
申请号：US11252878
申请日：2005-10-19
申请人： Uwe Wellhausen , Henry Heidemeyer , Joern Regul
发明人： Uwe Wellhausen , Henry Heidemeyer , Joern Regul
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/10826 , H01L27/10844 , H01L29/785
摘要： The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.
摘要翻译：本发明涉及一种形成具有介电材料的半导体器件的隔离沟槽的方法，以及在存储器件中形成隔离沟槽的方法。

9. 发明申请

US20070037334A1 Memory device and method of manufacturing a memory device 失效
标题翻译：存储器件和制造存储器件的方法
公开(公告)号：US20070037334A1
公开(公告)日：2007-02-15
申请号：US11203927
申请日：2005-08-15
申请人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
发明人： Klaus Muemmler , Stefan Tegen , Peter Baars , Joern Regul
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L28/90 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.
摘要翻译：本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。牺牲层在保持在周边部分的同时从阵列部分选择性地移除。这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

10. 发明申请

US20050260812A1 Memory cell having a trench capacitor and method for fabricating a memory cell and trench capacitor 审中-公开
标题翻译：具有沟槽电容器的存储单元和用于制造存储单元和沟槽电容器的方法
公开(公告)号：US20050260812A1
公开(公告)日：2005-11-24
申请号：US11123822
申请日：2005-05-06
申请人： Christian Kapteyn , Joern Regul
发明人： Christian Kapteyn , Joern Regul
IPC分类号： H01L27/108 , H01L21/8234 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10867
摘要： A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first capacitor dielectric, a second capacitor electrode, a second capacitor dielectric and third capacitor electrode, includes connecting the first and third capacitor electrodes. The first and third capacitor electrodes are formed by conformal deposition methods, whereas the first capacitor dielectric, the second capacitor electrode and the second capacitor dielectric are formed by nonconformal deposition methods.
摘要翻译：公开了一种具有沟槽电容器，沟槽电容器和方法的存储单元。在一个实施例中，制造具有第一电容器电极，第一电容器电介质，第二电容器电极，第二电容器电介质和第三电容器电极的沟槽电容器的方法包括连接第一和第三电容器电极。第一和第三电容器电极通过共形沉积方法形成，而第一电容器电介质，第二电容器电极和第二电容器电介质通过非共形沉积方法形成。

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