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1. 发明授权

US06678186B2 Row decoded biasing of sense amplifier for improved one's margin 有权
标题翻译：读出放大器的行解码偏置，提高了余量
公开(公告)号：US06678186B2
公开(公告)日：2004-01-13
申请号：US10216990
申请日：2002-08-12
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other.
摘要翻译：提供了一种用于改善存储器电路中的读出放大器操作的结构和方法。本发明的说明性方法包括对在存储器阵列（外围电路）中的行驱动器接缝运行的行地址信号（即，RA123 ，LPHe ，LPHo ）进行预解码，并对其进行解码读出放大器间隙中的地址信号。完成解码以激发上升读出放大器间隙的信号，并将读出放大器偏置在一个方向或另一个方向上发射。

2. 发明授权

US06236606B1 Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06236606B1
公开(公告)日：2001-05-22
申请号：US09517028
申请日：2000-03-02
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C702
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”. A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

3. 发明授权

US06410385B1 ROM-embedded-DRAM 有权
公开(公告)号：US06410385B1
公开(公告)日：2002-06-25
申请号：US09833706
申请日：2001-04-13
申请人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
发明人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
IPC分类号： H01L218242
摘要： A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

4. 发明授权

US6134137A Rom-embedded-DRAM 失效
标题翻译： ROM嵌入式DRAM
公开(公告)号：US6134137A
公开(公告)日：2000-10-17
申请号：US127042
申请日：1998-07-31
申请人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
发明人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
IPC分类号： G11C11/00 , G11C11/24 , G11C11/404 , G11C17/12 , H01L21/8242 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/10852 , G11C11/005 , G11C11/24 , G11C11/404 , G11C17/12 , H01L27/105 , H01L27/10891 , H01L27/10844 , H01L27/11213 , H01L27/1122
摘要： A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only "1" or to the wordline of an adjacent cell to create a read only "0".
摘要翻译：通过在DRAM制造工艺中改变单个掩模将ROM嵌入到DRAM单元的阵列内，以便将DRAM电容器下电极选择性地短路到其自己的字线以创建只读“1”或相邻单元的字线创建只读“0”。

5. 发明授权

US06301178B1 Reduced cell voltage for memory device 有权
标题翻译：降低存储器件的电池电压
公开(公告)号：US06301178B1
公开(公告)日：2001-10-09
申请号：US09575964
申请日：2000-05-23
申请人： Scott J. Derner , Patrick J. Mullarkey
发明人： Scott J. Derner , Patrick J. Mullarkey
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C7/062
摘要： A memory cell stores a logical “1” at a reduced voltage of Vcc/2 with a cell-plate voltage of Vcc/4. A pair of complementary digit lines are initially biased to Vcc/2. Because the digit lines are biased to Vcc/2 and a “1” is stored as Vcc/2, no voltage delta appears on the digit line when the access transistor is turned on. A sense amplifier is biased to favor a logical “1” if there is no voltage differential between the digit lines in order for the data sense amplifier to correctly interpret having no voltage delta as a logical “1”. The row address is used to determine which digit line has the cell charge and which digit line is the reference. Using this approach, the gate voltages of the access device and of the isolation device do not have to be higher than Vcc. The use of lower cell voltage produces immediate gains in static refresh times due to the reduced leakage currents.
摘要翻译：存储单元以Vcc / 2的降低电压以Vcc / 4的单元板电压存储逻辑“1”。一对互补数字线最初偏向Vcc / 2。由于数字线被偏置到Vcc / 2，“1”被存储为Vcc / 2，当存取晶体管导通时，数字线上不出现电压增益。如果数字线之间没有电压差，则读出放大器被偏置以有利于逻辑“1”，以便数据读出放大器正确解释没有电压增量为逻辑“1”。行地址用于确定哪个数字线具有单元电荷，哪个数字线是参考。使用这种方法，接入装置和隔离装置的栅极电压不必高于Vcc。由于漏电流的降低，使用较低电池电压会在静态刷新时间内产生即时增益。

6. 发明授权

US06243285B1 ROM-embedded-DRAM 有权
公开(公告)号：US06243285B1
公开(公告)日：2001-06-05
申请号：US09559832
申请日：2000-04-28
申请人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
发明人： Casey R. Kurth , Scott J. Derner , Patrick J. Mullarkey
IPC分类号： G11C1124
CPC分类号： H01L27/10852 , G11C11/005 , G11C11/24 , G11C11/404 , G11C17/12 , H01L27/105 , H01L27/10844 , H01L27/10891 , H01L27/11213 , H01L27/1122
摘要： A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

7. 发明授权

US06192446B1 Memory device with command buffer 有权
标题翻译：具有命令缓冲区的内存设备
公开(公告)号：US06192446B1
公开(公告)日：2001-02-20
申请号：US09146412
申请日：1998-09-03
申请人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
发明人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
IPC分类号： G06F1200
CPC分类号： G11C7/1072
摘要： A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.
摘要翻译：存储器件包括存储器阵列，多条外部线，命令缓冲器和控制逻辑。多个外部线路适于接收外部命令。命令缓冲器适于存储至少一个命令缓冲器条目。控制逻辑耦合到多条外部线路和命令缓冲器。控制逻辑适于基于命令缓冲器条目和外部命令之一访问存储器阵列。提供了一种向存储器件提供命令的方法。存储器件包括命令缓冲器，控制逻辑和存储器阵列。该方法包括从命令缓冲区读取第一缓冲命令。第一个缓冲命令提供给控制逻辑。基于第一个缓冲命令访问存储器阵列。

8. 发明授权

US6111803A Reduced cell voltage for memory device 有权
标题翻译：降低存储器件的电池电压
公开(公告)号：US6111803A
公开(公告)日：2000-08-29
申请号：US385478
申请日：1999-08-30
申请人： Scott J. Derner , Patrick J. Mullarkey
发明人： Scott J. Derner , Patrick J. Mullarkey
IPC分类号： G11C7/06 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/062
摘要： A memory cell stores a logical "1" at a reduced voltage of V.sub.CC /2 with a cell-plate voltage of V.sub.CC /4. A pair of complementary digit lines are initially biased to V.sub.CC /2. Because the digit lines are biased to V.sub.CC /2 and a "1" is stored as V.sub.CC /2, no voltage delta appears on the digit line when the access transistor is turned on. A sense amplifier is biased to favor a logical "1" if there is no voltage differential between the digit lines in order for the data sense amplifier to correctly interpret having no voltage delta as a logical "1". The row address is used to determine which digit line has the cell charge and which digit line is the reference. Using this approach, the gate voltages of the access device and of the isolation device do not have to be higher than V.sub.CC. The use of lower cell voltage produces immediate gains in static refresh times due to the reduced leakage currents.
摘要翻译：存储单元以VCC / 2的电池板电压在VCC / 2的降低电压下存储逻辑“1”。一对互补数字线最初偏置到VCC / 2。由于数字线偏置到VCC / 2，“1”被存储为VCC / 2，当存取晶体管导通时，数字线上不出现电压增益。如果数字线之间没有电压差，则读出放大器被偏置以有利于逻辑“1”，以便数据读出放大器正确解释没有电压增量为逻辑“1”。行地址用于确定哪个数字线具有单元电荷，哪个数字线是参考。使用这种方法，接入设备和隔离设备的栅极电压不必高于VCC。由于漏电流的降低，使用较低电池电压会在静态刷新时间内产生即时增益。

9. 发明授权

US06434072B1 Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06434072B1
公开(公告)日：2002-08-13
申请号：US09862694
申请日：2001-05-22
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C702
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”. A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

10. 发明授权

US06385691B2 Memory device with command buffer that allows internal command buffer jumps 有权
标题翻译：具有命令缓冲区的内存设备，允许内部命令缓冲区跳转
公开(公告)号：US06385691B2
公开(公告)日：2002-05-07
申请号：US09764502
申请日：2001-01-17
申请人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
发明人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
IPC分类号： G06F1200
CPC分类号： G11C7/1072
摘要： A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.
摘要翻译：存储器件包括存储器阵列，多条外部线，命令缓冲器和控制逻辑。多个外部线路适于接收外部命令。命令缓冲器适于存储至少一个命令缓冲器条目。控制逻辑耦合到多条外部线路和命令缓冲器。控制逻辑适于基于命令缓冲器条目和外部命令之一访问存储器阵列。提供了一种向存储器件提供命令的方法。存储器件包括命令缓冲器，控制逻辑和存储器阵列。该方法包括从命令缓冲区读取第一缓冲命令。第一个缓冲命令提供给控制逻辑。基于第一个缓冲命令访问存储器阵列。

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