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1. 发明授权

US07705628B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
标题翻译：可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器
公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
申请人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
发明人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译：具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。多个逻辑块中的每一个还包括一个或多个逻辑元件。逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

2. 发明授权

US07558812B1 Structures for LUT-based arithmetic in PLDs 有权
标题翻译：在PLD中基于LUT的算术的结构
公开(公告)号：US07558812B1
公开(公告)日：2009-07-07
申请号：US10723104
申请日：2003-11-26
申请人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
发明人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/575 , H03K19/177 , H03K19/17728
摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.
摘要翻译：可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个二进制输入信号的算术组合的多级。输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。所描述的LUT可以有效地执行算术，以及非算术函数。

3. 发明授权

US07287189B1 I/O configuration and reconfiguration trigger through testing interface 有权
标题翻译：通过测试界面进行I / O配置和重新配置触发
公开(公告)号：US07287189B1
公开(公告)日：2007-10-23
申请号：US10603888
申请日：2003-06-25
申请人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
发明人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
IPC分类号： G06F11/00
CPC分类号： G01R31/318572
摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.
摘要翻译：可重构设备在测试期间从诊断接口加载I / O配置信息。该设备包括用于与其他设备通信值的可配置I / O连接。诊断接口将I / O连接的值传送给测试仪。设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式接口，从而修改I / O连接的配置。该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。诊断接口可以是JTAG接口。

4. 发明授权

US08788550B1 Structures for LUT-based arithmetic in PLDs 有权
标题翻译：在PLD中基于LUT的算术的结构
公开(公告)号：US08788550B1
公开(公告)日：2014-07-22
申请号：US12484010
申请日：2009-06-12
申请人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
发明人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/575 , H03K19/177 , H03K19/17728
摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.
摘要翻译：可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个二进制输入信号的算术组合的多级。输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。所描述的LUT可以有效地执行算术，以及非算术函数。

5. 发明授权

US07512849B1 Reconfigurable programmable logic system with configuration recovery mode 有权
标题翻译：具有配置恢复模式的可重构可编程逻辑系统
公开(公告)号：US07512849B1
公开(公告)日：2009-03-31
申请号：US11294715
申请日：2005-12-05
申请人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
发明人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
IPC分类号： G01R31/28 , G06F7/38
CPC分类号： G01R31/318516
摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.
摘要翻译：可编程逻辑系统包括可重新配置的可编程逻辑器件和存储至少两种配置的配置存储器。首先加载默认配置，然后加载所需的用户应用程序配置。如果用户应用程序配置失败，系统将保存有关故障的数据，然后返回到默认配置进行恢复。读取故障数据后，默认配置会导致调用操作员进行干预，或者在配置存储器中可用时加载不同的（例如，以前的）配置。该系统在用户可以远程更新配置的情况下特别有用。在另一种模式下，系统仅存储用户配置（首先被加载）和默认配置。如果新加载的配置失败，则加载默认配置，并向操作员发出信号，或者在加载不同配置时采取其他操作。

6. 发明授权

US07000161B1 Reconfigurable programmable logic system with configuration recovery mode 失效
公开(公告)号：US07000161B1
公开(公告)日：2006-02-14
申请号：US10270800
申请日：2002-10-11
申请人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
发明人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

7. 发明申请

US20100026340A1 User-Accessible Freeze-Logic for Dynamic Power Reduction and Associated Methods 有权
标题翻译：用户可访问的冻结逻辑用于动态功率降低和相关方法
公开(公告)号：US20100026340A1
公开(公告)日：2010-02-04
申请号：US12577061
申请日：2009-10-09
申请人： Michael D. Hutton , Andy L. Lee
发明人： Michael D. Hutton , Andy L. Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17784
摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
摘要翻译：可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

8. 发明授权

US07605603B1 User-accessible freeze-logic for dynamic power reduction and associated methods 有权
标题翻译：用户可访问的冻结逻辑，用于动态功率降低和相关方法
公开(公告)号：US07605603B1
公开(公告)日：2009-10-20
申请号：US12040100
申请日：2008-02-29
申请人： Michael D. Hutton , Andy L. Lee
发明人： Michael D. Hutton , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17784
摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
摘要翻译：可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

9. 发明授权

US09165931B1 Apparatus for field-programmable gate array with configurable architecture and associated methods 有权
标题翻译：具有可配置架构和相关方法的现场可编程门阵列的装置
公开(公告)号：US09165931B1
公开(公告)日：2015-10-20
申请号：US14187185
申请日：2014-02-21
申请人： Herman Schmit , David Lewis , Michael D. Hutton , Dana How , Andy L. Lee
发明人： Herman Schmit , David Lewis , Michael D. Hutton , Dana How , Andy L. Lee
IPC分类号： H01L27/115 , G06F17/50 , H01L27/105
CPC分类号： G06F17/5054 , G06F15/7867 , H01L27/115 , H03K19/17728
摘要： An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.
摘要翻译：集成电路（IC）包括IC的通用基板和IC的变体。 IC还包括在衬底上方制造的第一组互连层。第一组互连层用于将IC的可编程互连件耦合到衬底中的第一电路。 IC还包括在衬底上方制造的第二组互连层。第二组互连层用于通过选择性地将可编程互连连接到衬底中的第二电路来区分IC的特征与IC的变体。

10. 发明授权

US07839165B2 User-accessible freeze-logic for dynamic power reduction and associated methods 有权
标题翻译：用户可访问的冻结逻辑，用于动态功率降低和相关方法
公开(公告)号：US07839165B2
公开(公告)日：2010-11-23
申请号：US12577061
申请日：2009-10-09
申请人： Michael D. Hutton , Andy L. Lee
发明人： Michael D. Hutton , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17784
摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
摘要翻译：可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

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