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    • 5. 发明授权
    • Plasma processing apparatus
    • 等离子体处理装置
    • US6033481A
    • 2000-03-07
    • US225971
    • 1999-01-06
    • Ken'etsu YokogawaTetsuo OnoKazunori TsujimotoNaoshi ItabashiMasahito MoriShinichi TachiKeizo Suzuki
    • Ken'etsu YokogawaTetsuo OnoKazunori TsujimotoNaoshi ItabashiMasahito MoriShinichi TachiKeizo Suzuki
    • C23C16/00H01J37/32
    • H01J37/3222H01J37/32082H01J37/32678H01J2237/3341
    • A plasma processing apparatus in which power consumption is reduced, which can generate uniform plasma in a large range and in which minute processing in high etching selectivity and in high aspect ratio is enabled is disclosed. High density plasma is generated in a vacuum vessel housing a processed sample utilizing an electron cyclotron resonance phenomenon caused by an electromagnetic wave in an ultra-high frequency band and a magnetic field and the surface of the processed sample is etched using this plasma. An electromagnetic wave in an ultra-high frequency band for generating plasma is radiated from a planar conductive plate consisting of graphite or silicon which is arranged opposite to the surface of the processed sample into space inside the vacuum vessel. High density plasma in the low degree of dissociation can be generated by using an electromagnetic wave in an ultra-high frequency band and as a result, the controllability of etching reaction can be enhanced. Further, a radical effective in etching can be increased by reaction between the surface of a planar conductive plate for radiating an electromagnetic wave and plasma.
    • 公开了能够在大范围内产生均匀的等离子体并能够实现高蚀刻选择性和高纵横比的微小加工的功耗降低的等离子体处理装置。 利用由超高频带和磁场中的电磁波引起的电子回旋共振现象,在容纳加工样品的真空容器中产生高密度等离子体,并且使用该等离子体蚀刻处理样品的表面。 用于产生等离子体的超高频带中的电磁波从由石墨或硅组成的平面导电板辐射,该导电板与被处理样品的表面相对地设置在真空容器内部的空间中。 通过在超高频带中使用电磁波可以产生低解离度的高密度等离子体,结果可以提高蚀刻反应的可控性。 此外,通过用于辐射电磁波的平面导电板的表面与等离子体之间的反应可以增加蚀刻中有效的自由基。
    • 7. 发明授权
    • Method of manufacturing semiconductor devices
    • 制造半导体器件的方法
    • US06673685B2
    • 2004-01-06
    • US10083397
    • 2002-02-27
    • Masahito MoriNaoshi ItabashiMasaru Izawa
    • Masahito MoriNaoshi ItabashiMasaru Izawa
    • H01L21336
    • H01L21/28123H01L21/31138H01L21/32136H01L21/32137H01L21/32139
    • A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment. The process can be implemented to provide the effects of forming a gate no longer than 50 nm (beyond the limit of exposure) without restrictions on the resist thickness; reducing contamination resulting from transfer of wafers from one step to next, thereby improving yields; preventing resist from hydrolysis by ArF laser, thereby reducing roughening which adversely affects the gate width; and ensuring stable yields despite variation in dimensions and contamination owing to the additional dry cleaning step and feed-forward control based on CD inspection and contamination inspection.
    • 用于经济有效地制造不超过50nm的栅电极的方法,其超出了曝光的限度,其特征在于组合执行的具有高抗蚀剂选择性的栅电极修整和掩模修剪。 该方法还优选的特征在于在真空环境中进行修整和干燥清洁,并且还可以包括在真空环境中检查尺寸和污染的步骤。 可以实现该过程以提供形成栅极不超过50nm(超过曝光极限)而不限制抗蚀剂厚度的效果; 减少晶片从一步转移到下一步导致的污染,从而提高产量; 防止ArF激光器的抗水解,从而减少对栅极宽度有不利影响的粗糙化; 并确保稳定的产量,尽管由于额外的干洗步骤和基于CD检查和污染检查的前馈控制而导致尺寸和污染的变化。