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1. 发明授权

US07581120B1 System and method for providing multi-point calibration of an adaptive voltage scaling system 有权
标题翻译：用于提供自适应电压缩放系统的多点校准的系统和方法
公开(公告)号：US07581120B1
公开(公告)日：2009-08-25
申请号：US11134997
申请日：2005-05-23
申请人： Mark Hartman , James T. Doyle , Dragan Maksimovic , Pasi Salmi , Juha Pennanen , Sandeep Dhar
发明人： Mark Hartman , James T. Doyle , Dragan Maksimovic , Pasi Salmi , Juha Pennanen , Sandeep Dhar
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.
摘要翻译：公开了一种用于提供自适应电压缩放（AVS）系统的多点校准的系统和方法。提供了多点校准表中的多个参考校准码（RCC）。每个代码与自适应电压缩放（AVS）系统的时钟频率之一相关联。本发明通过针对自适应电压缩放（AVS）系统的每个工作点（时钟频率）校准参考校准代码（RCC）来提供多点校准。

2. 发明授权

US08151125B1 System and method for providing multi-point calibration of an adaptive voltage scaling system 有权
标题翻译：用于提供自适应电压缩放系统的多点校准的系统和方法
公开(公告)号：US08151125B1
公开(公告)日：2012-04-03
申请号：US12462888
申请日：2009-08-11
申请人： Mark Hartman , James T. Doyle , Dragan Maksimovic , Pasi Salmi , Juha Pennanen , Sandeep Dhar
发明人： Mark Hartman , James T. Doyle , Dragan Maksimovic , Pasi Salmi , Juha Pennanen , Sandeep Dhar
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.
摘要翻译：公开了一种用于提供自适应电压缩放（AVS）系统的多点校准的系统和方法。提供了多点校准表中的多个参考校准码（RCC）。每个代码与自适应电压缩放（AVS）系统的时钟频率之一相关联。本发明通过针对自适应电压缩放（AVS）系统的每个工作点（时钟频率）校准参考校准代码（RCC）来提供多点校准。

3. 发明授权

US07493149B1 Method and system for minimizing power consumption in mobile devices using cooperative adaptive voltage and threshold scaling 有权
标题翻译：使用协作自适应电压和阈值缩放来最小化移动设备功耗的方法和系统
公开(公告)号：US07493149B1
公开(公告)日：2009-02-17
申请号：US10106428
申请日：2002-03-26
申请人： James T. Doyle , Dragan Maksimovic
发明人： James T. Doyle , Dragan Maksimovic
IPC分类号： H04M1/73
CPC分类号： G06F1/3203 , H04W52/0258 , Y02D70/142 , Y02D70/164
摘要： A method for minimizing power consumption in a mobile device using cooperative adaptive voltage and threshold scaling is provided that includes receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage. A clock signal is received. The clock signal is propagated through a timing comparison circuit. An output of the timing comparison circuit is examined. A determination is made regarding whether to request more power based on the output of the timing comparison circuit. A voltage control signal is sent to request more power when a determination is made to request more power based on the output of the timing comparison circuit.
摘要翻译：提供一种使用协作自适应电压和阈值缩放来最小化移动设备中的功耗的方法，其包括接收电源电压，PMOS反向偏置电压和NMOS背置偏置电压。接收时钟信号。时钟信号通过定时比较电路传播。检查定时比较电路的输出。确定是否基于定时比较电路的输出请求更多的功率。当确定基于定时比较电路的输出请求更多功率时，发送电压控制信号以请求更多功率。

4. 发明授权

US06900697B1 Method and system for providing power management in a radio frequency power amplifier by dynamically adjusting supply and bias conditions 有权
标题翻译：通过动态调整供电和偏置条件，在射频功率放大器中提供电源管理的方法和系统
公开(公告)号：US06900697B1
公开(公告)日：2005-05-31
申请号：US10160281
申请日：2002-05-31
申请人： James T. Doyle , Dragan Maksimovic , Yushan Li
发明人： James T. Doyle , Dragan Maksimovic , Yushan Li
IPC分类号： H03F1/02 , H03F3/04
CPC分类号： H03F1/0222 , H03F1/0233 , H03F1/0266 , H03F1/0272
摘要： A method for providing power management in a radio frequency power amplifier is provided. An input voltage is received. A digital power supply signal is generated. From the input voltage, a regulated power supply signal is generated based on the digital power supply signal.
摘要翻译：提供了一种在射频功率放大器中提供电源管理的方法。接收输入电压。产生数字电源信号。根据输入电压，基于数字电源信号产生稳定的电源信号。

5. 发明授权

US06914487B1 Method and system for providing power management in a radio frequency power amplifier using adaptive envelope tracking 有权
标题翻译：使用自适应包络跟踪在射频功率放大器中提供电源管理的方法和系统
公开(公告)号：US06914487B1
公开(公告)日：2005-07-05
申请号：US10417566
申请日：2003-04-17
申请人： James T. Doyle , Dragan Maksimovic , Yushan Li
发明人： James T. Doyle , Dragan Maksimovic , Yushan Li
IPC分类号： H03F1/02 , H03F3/04
CPC分类号： H03F1/0233 , H03F1/0222 , H03F2200/102
摘要： A method for providing power management in a radio frequency power amplifier using adaptive envelope tracking is provided that includes receiving an input voltage. A power control signal is received. A feedback signal is received. An amplifier input signal is received. From the input voltage, a regulated power supply signal is generated based on the power control signal, the feedback signal, and the amplifier input signal.
摘要翻译：提供了一种使用自适应包络跟踪在射频功率放大器中提供功率管理的方法，其包括接收输入电压。接收功率控制信号。接收到反馈信号。接收放大器输入信号。根据输入电压，基于功率控制信号，反馈信号和放大器输入信号产生稳定的电源信号。

6. 发明授权

US08253405B2 High speed voltage regulator with integrated loseless current sensing 有权
标题翻译：具有集成无电流电流检测功能的高速电压调节器
公开(公告)号：US08253405B2
公开(公告)日：2012-08-28
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G05F1/00
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

7. 发明申请

US20100164477A1 HIGH SPEED VOLTAGE REGULATOR WITH INTEGRATED LOSELESS CURRENT SENSING 有权
标题翻译：具有集成无电流电流传感的高速电压调节器
公开(公告)号：US20100164477A1
公开(公告)日：2010-07-01
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G01R19/00 , G05F1/10
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

8. 发明授权

US06771101B1 CMOS reference circuit using field effect transistors in lieu of resistors and diodes 有权
标题翻译： CMOS参考电路采用场效应晶体管代替电阻和二极管
公开(公告)号：US06771101B1
公开(公告)日：2004-08-03
申请号：US10226523
申请日：2002-08-22
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03L700
CPC分类号： G05F3/30 , Y10S323/901
摘要： A CMOS reference circuit using field effect transistors (FETs) is described. A first plurality of FETs is coupled in series, source node to drain node. A second plurality of FETs is also coupled in series, source node to drain node. The first and second plurality of FETs are coupled such that a specified total voltage drop across the first plurality of FETs is realizable. The combination of the first and second plurality of FETs are usable as a replacement for a resistor. The circuit can also include a FET configured so that it is usable as a replacement for a diode.
摘要翻译：描述了使用场效应晶体管（FET）的CMOS参考电路。第一组多个FET串联耦合，源节点到漏极节点。第二组多个FET串联耦合，源节点到漏极节点。第一和第二多个FET被耦合，使得跨越第一多个FET的规定的总电压降是可实现的。第一和第二多个FET的组合可用作电阻器的替代。该电路还可以包括被配置为使得其可用作二极管的替代物的FET。

9. 发明授权

US06629254B1 Clocking architecture to compensate a delay introduced by a signal buffer 有权
标题翻译：时钟架构来补偿由信号缓冲器引入的延迟
公开(公告)号：US06629254B1
公开(公告)日：2003-09-30
申请号：US09607565
申请日：2000-06-29
申请人： Syed R. Naqvi , James T. Doyle
发明人： Syed R. Naqvi , James T. Doyle
IPC分类号： G06F112
CPC分类号： H03L7/0812 , G06F1/10 , H03L7/06
摘要： An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.
摘要翻译：一种装置包括存储器缓冲器，第一信号缓冲器，锁定环路电路和反馈电路。存储器缓冲器响应于第一时钟信号向存储器缓冲器的输出端提供数据信号。第一信号缓冲器耦合在存储器缓冲器的输出端和总线的数据线之间。第一个信号缓冲器引入第一个延迟。锁定环路电路提供第一时钟信号以建立第二时钟信号的相位和第三时钟信号的相位之间的预定关系。反馈电路响应于第一时钟信号产生第二时钟信号。反馈电路包括用于向第二时钟引入第二延迟的第二信号缓冲器，并且第二延迟与由第一信号缓冲器引入的第一延迟大致相同。

10. 发明授权

US6147548A Sub-bandgap reference using a switched capacitor averaging circuit 有权
标题翻译：使用开关电容平均电路的子带隙基准
公开(公告)号：US6147548A
公开(公告)日：2000-11-14
申请号：US441629
申请日：1999-11-16
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： G05F3/30 , G05F1/10
CPC分类号： G05F3/30
摘要： A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V.sub.be and an oppositely tracking (positive temperature coefficient) .DELTA.V.sub.be, and takes the average of two signals related to .DELTA.V.sub.be -V.sub.be to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the .DELTA.V.sub.be -V.sub.be signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the .DELTA.V.sub.be -V.sub.be circuitry operates with low headroom in part due to a n-well biasing scheme that lowers the effective threshold voltage of the p-channel FETs used in the loop amplifier.
摘要翻译：产生比硅的带隙电压小的参考电压的子带隙参考电路。电路产生负温度系数信号Vbe和相反的跟踪（正温度系数）DELTA Vbe，并且获得与DELTA Vbe-Vbe相关的两个信号的平均值，以得到硅的带隙电压的一半的温度补偿电压。该电路具有不等面积的电流镜，馈送用于使用低电源电压（小于1.5伏）产生DELTA Vbe-Vbe信号的二极管和电阻。标准CMOS实现在仅1伏特的电源电压和良好的温度系数下提供低功耗。平均电路可以由连续时分器或通过使用开关电容器技术来实现。在DELTA Vbe-Vbe电路中使用的环路放大器部分由于采用n阱偏置方案，具有较低的余量运行，降低了环路放大器中使用的p沟道FET的有效阈值电压。

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