专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060286736A1 Method for forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060286736A1
公开(公告)日：2006-12-21
申请号：US11152931
申请日：2005-06-15
申请人： Marius Orlowski , Brian Goolsby
发明人： Marius Orlowski , Brian Goolsby
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823418
摘要： An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
摘要翻译：通过形成覆盖多个晶体管位置的第一和第二层来形成电子器件。执行蚀刻以去除第一层和第二层的部分以暴露多个晶体管位置的一部分，而第一层和第二层的其它部分保留以保护其他晶体管位置。随后，暴露的晶体管位置的源极/漏极位置与第二层的剩余部分一起被蚀刻。通过使用涉及第一层的端点检测技术去除第二层的部分来基本上终止蚀刻。随后在源极/漏极凹槽中形成外延层，以在晶体管位置的沟道区上提供应力。

2. 发明申请

US20170155045A1 Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses 审中-公开
公开(公告)号：US20170155045A1
公开(公告)日：2017-06-01
申请号：US15365445
申请日：2016-11-30
申请人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
发明人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/149 , G11C11/5614 , G11C13/0011 , G11C2013/0078 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

3. 发明授权

US08552501B2 Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device 有权
标题翻译：形成用于反向T沟道场效应晶体管器件的反相T形沟道结构的方法
公开(公告)号：US08552501B2
公开(公告)日：2013-10-08
申请号：US13447369
申请日：2012-04-16
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7854 , H01L29/66795 , H01L29/78687
摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.
摘要翻译：形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括半导体衬底，半导体衬底上的第一半导体材料的第一层和第二层在第一层上的第二半导体材料。选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。

4. 发明授权

US08202798B2 Improvements for reducing electromigration effect in an integrated circuit 有权
标题翻译：降低集成电路中电迁移效应的改进
公开(公告)号：US08202798B2
公开(公告)日：2012-06-19
申请号：US12675242
申请日：2007-09-20
申请人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
发明人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
摘要翻译：一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动的原子到第二个区域。

5. 发明申请

US20100044762A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF 审中-公开
标题翻译：形成半导体器件及其结构的方法
公开(公告)号：US20100044762A1
公开(公告)日：2010-02-25
申请号：US12605556
申请日：2009-10-26
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L29/78 , H01L29/772
CPC分类号： H01L29/78684 , H01L29/66818 , H01L29/785
摘要： A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.
摘要翻译：非平面半导体器件（10）从硅片（42）开始。将锗源（例如24,26,28,30,32）提供给翅片（42）。一些实施例可以使用沉积来提供锗; 一些实施例可以使用离子注入（30）来提供锗; 也可以使用其它方法来提供锗。然后将翅片（42）氧化以在翅片（36）中形成硅锗通道区域。在一些实施例中，整个鳍（42）从硅转变为硅锗。可以使用一个或多个翅片（36）来形成非平面半导体器件，例如FINFET，MIGFET，三栅极晶体管或多栅极晶体管。

6. 发明申请

US20080006880A1 METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件中移动性增强的方法和装置
公开(公告)号：US20080006880A1
公开(公告)日：2008-01-10
申请号：US11857122
申请日：2007-09-18
申请人： Marius Orlowski , Suresh Venkatesan
发明人： Marius Orlowski , Suresh Venkatesan
IPC分类号： H01L29/76
CPC分类号： H01L29/7846 , H01L29/0653 , H01L29/1054 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.
摘要翻译：提出了一种在晶体管的沟道区域中提供迁移率增强的方法和装置。在一个实施例中，沟槽区域（18）形成在双轴向应力的衬底上。源极（30）和漏极（32）区域形成在衬底上。源极和漏极区域向双向应力通道区域提供额外的单轴应力。单向应力和双轴向应力对于P沟道晶体管是压缩的，对于N沟道晶体管是拉伸的。两种晶体管类型都可以包含在同一集成电路中。

7. 发明申请

US20070235807A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US20070235807A1
公开(公告)日：2007-10-11
申请号：US11742955
申请日：2007-05-01
申请人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

8. 发明申请

US20070218628A1 Electronic device including a semiconductor fin and a process for forming the electronic device 有权
标题翻译：包括半导体鳍片的电子设备和用于形成电子设备的工艺
公开(公告)号：US20070218628A1
公开(公告)日：2007-09-20
申请号：US11375890
申请日：2006-03-15
申请人： Marius Orlowski , Suresh Venkatesan
发明人： Marius Orlowski , Suresh Venkatesan
IPC分类号： H01L21/8242
CPC分类号： H01L27/1211 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L29/66795 , H01L29/785
摘要： An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.
摘要翻译：电子器件可以包括基极层，半导体层和与半导体层间隔开并覆盖半导体层的第一半导体鳍片。在特定实施例中，第二半导体鳍片可以包括半导体层的一部分。另一方面，形成电子器件的工艺可以包括提供一种工件，其包括基底层，覆盖并与基底层间隔开的第一半导体层，覆盖在第二半导体层上的绝缘层和位于第二半导体层之间的绝缘层第一半导体层和第二半导体层。该工艺还可以包括去除第二半导体层的一部分以形成第一半导体鳍片，以及形成覆盖在第一半导体鳍片上的导电构件。

9. 发明申请

US20070176247A1 MOS device with multi-layer gate stack 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US20070176247A1
公开(公告)日：2007-08-02
申请号：US11343623
申请日：2006-01-30
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/94
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.
摘要翻译：为半导体器件提供了方法和装置。该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层，例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动杂质，例如氧气，朝向衬底。

10. 发明申请

US20060240650A1 Semiconductor device having a plurality of different layers and method therefor 有权
标题翻译：具有多个不同层的半导体器件及其方法
公开(公告)号：US20060240650A1
公开(公告)日：2006-10-26
申请号：US11111451
申请日：2005-04-21
申请人： Marius Orlowski , Vance Adams
发明人： Marius Orlowski , Vance Adams
IPC分类号： H01L21/425 , H01L29/768 , H01L27/148 , H01L29/74
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式