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1. 发明申请

WO2012097046A1 LDPC MULTI-DECODER ARCHITECTURES 审中-公开
标题翻译： LDPC多解码器架构
公开(公告)号：WO2012097046A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/020910
申请日：2012-01-11
申请人： MARVELL WORLD TRADE LTD. , VARNICA, Nedeljko , BURD, Gregory
发明人： VARNICA, Nedeljko , BURD, Gregory
IPC分类号： H03M13/37 , H03M13/11
CPC分类号： H03M13/1108 , H03M13/1117 , H03M13/1128 , H03M13/1131 , H03M13/1137 , H03M13/116 , H03M13/2909 , H03M13/3707
摘要： Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix. The super matrix corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder. The super-parity- check matrix includes n parity check matrices. The parity check matrices include x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows corresponding to nx check node processing elements and ny columns corresponding to ny bit node processing elements. The numbers n, x, and y are selected so that ny codeword bits corresponding to the super-parity-check matrix can be processed in single time unit by the high throughput decoder and y codeword bits corresponding to the super-parity- check matrix can be processed in a single time unit by the low throughput decoder.
摘要翻译：描述了与LDPC解码器架构相关联的系统，方法和其他实施例。根据一个实施例，一种装置包括超奇偶校验矩阵。超矩阵对应于低密度奇偶校验（LDPC）码矩阵的至少一部分。超奇偶校验矩阵耦合到高吞吐量LDPC解码器和低吞吐量LDPC解码器。超奇偶校验矩阵包括n个奇偶校验矩阵。奇偶校验矩阵包括对应于x校验节点处理元素的x行和对应于y位节点处理元素的y列。因此，超奇偶校验矩阵包括对应于n×校验节点处理元素的nx行和对应于ny位节点处理元素的ny列。选择数字n，x和y，使得与超奇偶校验矩阵相对应的ny码字比特可以由高吞吐量解码器以及对应于超奇偶校验矩阵的y码字比特以单个时间单位处理由低吞吐量解码器以单个时间单位进行处理。

2. 发明申请

WO2015048677A1 GENERATING POSITION ERROR SIGNAL BASED ON DATA TRACKS FOR MAGNETIC DATA STORAGE 审中-公开
标题翻译：基于数据轨迹生成磁位数据存储的位置误差信号
公开(公告)号：WO2015048677A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/058116
申请日：2014-09-29
申请人： MARVELL WORLD TRADE LTD. , OBERG, Mats , BURD, Gregory
发明人： OBERG, Mats , BURD, Gregory
IPC分类号： G11B5/55 , G11B5/596
CPC分类号： G11B5/59622 , G11B5/5547 , G11B5/59611 , G11B5/59627 , G11B5/5965 , G11B20/10212 , G11B20/10305
摘要： A hard disk drive circuit includes first and second inter-track interference detection modules. The first inter-track interference detection module is configured to generate a first measured inter-track interference value based on a first read signal from a first read sensor positioned over a magnetic medium. The second inter-track interference detection module is configured to generate a second measured inter-track interference value based on a second read signal from a second read sensor positioned over the magnetic medium. A position error signal generation module is configured to generate a position error signal based on the first measured inter-track interference value and the second measured inter-track interference value. An arm control module is configured to control rotation of an arm in response to the position error signal. The first read sensor and the second read sensor are located at a distal end of the arm.
摘要翻译：硬盘驱动器电路包括第一和第二轨道间干扰检测模块。第一轨道间干扰检测模块被配置为基于来自位于磁介质上的第一读取传感器的第一读取信号来生成第一测量的轨道间干扰值。第二轨道间干扰检测模块被配置为基于来自位于磁介质上的第二读取传感器的第二读取信号来生成第二测量的轨道间干扰值。位置误差信号生成模块被配置为基于第一测量的轨道间干扰值和第二测量的轨道间干扰值来生成位置误差信号。臂控制模块被构造成响应于位置误差信号来控制臂的旋转。第一读取传感器和第二读取传感器位于手臂的远端。

3. 发明申请

WO2011028802A1 SYSTEMS AND METHODS FOR COMPRESSING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DRIVES 审中-公开
标题翻译：用于压缩非易失性半导体存储器驱动器中的数据的系统和方法
公开(公告)号：WO2011028802A1
公开(公告)日：2011-03-10
申请号：PCT/US2010/047533
申请日：2010-09-01
申请人： MARVELL WORLD TRADE LTD. , BURD, Gregory , YANG, Xueshi
发明人： BURD, Gregory , YANG, Xueshi
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F12/0238 , G06F3/0608 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0623 , G06F3/064 , G06F3/0658 , G06F3/0679
摘要： A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM.
摘要翻译：非易失性半导体存储器（NVSM）存储系统包括被配置为从主机接口接收主机数据扇区（HDS）的NVSM驱动器接口。缓冲器管理模块被配置为将HDS存储在缓冲器中。压缩模块被配置为压缩HDS以产生不同长度的压缩HDS。驱动数据扇区（DDS）生成模块被配置为向压缩的HDS添加有害数据以产生DDS。 DDS存储在NVSM中。

4. 发明申请

WO2012106255A1 MAPPING DATA TO NON-VOLATILE MEMORY 审中-公开
标题翻译：将数据映射到非易失性存储器
公开(公告)号：WO2012106255A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023165
申请日：2012-01-30
申请人： MARVELL WORLD TRADE LTD. , CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
发明人： CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure that includes a plurality of multi- level memory cells. The described system includes a controller configured to map a data segment to the plurality of multi -level memory cells. A first portion of a first set of consecutive bits of a data segment (sector 1) is mapped to a first page (LSBpage) associated with the plurality of multi -level memory cells. A second portion of the first set of consecutive bits of the data segment (sectorl) is mapped to a second page (MSB page) associated with the plurality of multi -level memory cells. A first portion of a second set of consecutive bits of the data segment (sector2) is mapped to the first page. A second portion of the second set of consecutive bits of the data segment is mapped to the second page. The first page is associated with bits of a first significance (LSB), and the second page is associated with bits of a second significance (MSB).
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括包括多个多级存储器单元的非易失性存储器结构。所描述的系统包括被配置为将数据段映射到多个多层存储器单元的控制器。数据段（扇区1）的第一组连续位的第一部分被映射到与多个多层存储器单元相关联的第一页（LSB页）。数据段（扇区1）的第一组连续位的第二部分被映射到与多个多层存储器单元相关联的第二页（MSB页）。数据段（扇区2）的第二组连续位的第一部分被映射到第一页。数据段的第二组连续位的第二部分被映射到第二页。第一页与第一有效位（LSB）的位相关联，并且第二页与第二有效位（MSB）的位相关联。

5. 发明申请

WO2008058082A2 ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS 审中-公开
标题翻译：用于记忆细胞的自适应读取和写入系统和方法
公开(公告)号：WO2008058082A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/083649
申请日：2007-11-05
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , BURD, Gregory
发明人： YANG, Xueshi , BURD, Gregory
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Adaptive memory read and write systems and methods are described herein that adapts to changes to threshold voltage distributions of memory cells as of result of, for example, the detrimental affects of repeated cycling operations of the memory cells. The novel systems may include at least multi-level memory cells, which may be multi-level flash memory cells, and a computation block operatively coupled to the multi-level memory cells. The computation block may be configured to compute optimal or near optimal mean and detection threshold values based, at least in part, on estimated mean and standard deviation values of level distributions of the multi-level memory cells. The optimal or near optimal mean and detection threshold values computed by the computation block may be subsequently used to facilitate writing and reading, respectively, of data to and from the multi-level memory cells.
摘要翻译：本文描述了自适应存储器读写系统和方法，其适应于存储器单元的阈值电压分布的变化，例如由于存储器单元的重复循环操作的有害影响。该新颖系统可以包括至少多级存储器单元，其可以是多级闪存单元，以及可操作地耦合到多级存储器单元的计算块。该计算块可以被配置为至少部分地基于多级存储器单元的级别分布的估计平均值和标准偏差值来计算最佳或近似最优的平均值和检测阈值。随后可以使用由计算块计算的最佳或接近最优的平均值和检测阈值，以便于分别向多层存储器单元写入和读取数据。

6. 发明申请

WO2014149738A1 SYSTEMS AND METHODS FOR MULTI-STAGE SOFT INPUT DECODING 审中-公开
标题翻译：用于多级软输入解码的系统和方法
公开(公告)号：WO2014149738A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/020644
申请日：2014-03-05
申请人： MARVELL WORLD TRADE LTD. , CHILAPPAGARI, Shashi, Kiran , BURD, Gregory
发明人： CHILAPPAGARI, Shashi, Kiran , BURD, Gregory
IPC分类号： H04L1/00 , G06F11/10 , H03M13/11 , H03M13/37
CPC分类号： G06F11/1068 , H03M13/1108 , H03M13/1111 , H03M13/1128 , H03M13/3707 , H04L1/0052
摘要： Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information.
摘要翻译：提供了解码数据的系统和方法。第一解码器尝试基于用于符号的硬判决输入对数据进行解码。当基于硬判决输入解码数据的尝试失败时，发送请求被发送用于符号的可靠性信息。接收电路接收符号的可靠性信息，第二解码器基于可靠性信息对数据进行解码。

7. 发明申请

WO2008036378A2 RELIABILITY METRIC GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING 审中-公开
标题翻译：基于TRLLIS的检测和/或解码的可靠性公制生成
公开(公告)号：WO2008036378A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/020423
申请日：2007-09-20
申请人： MARVELL WORLD TRADE LTD. , YANG, Shaohua , LOW, Seo-How , WU, Zining , BURD, Gregory
发明人： YANG, Shaohua , LOW, Seo-How , WU, Zining , BURD, Gregory
IPC分类号： H03M13/41
CPC分类号： H03M13/4153 , H03M13/098 , H03M13/2933 , H04L25/03203 , H04L25/067
摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology computes soft reliability information for each detected/decoded bit or codeword syndrome value.
摘要翻译：所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。在本发明的一个方面，所公开的技术为每个检测/解码的比特或码字综合征值计算软可靠性信息。

8. 发明申请

WO2007103317A1 SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING 审中-公开
标题翻译：使用奇偶校验交互实现更高编码率的系统和方法
公开(公告)号：WO2007103317A1
公开(公告)日：2007-09-13
申请号：PCT/US2007/005602
申请日：2007-03-05
申请人： MARVELL WORLD TRADE LTD. , TANG, Heng , BURD, Gregory , WU, Zining , CHAICHANAVONG, Panu
发明人： TANG, Heng , BURD, Gregory , WU, Zining , CHAICHANAVONG, Panu
IPC分类号： H03M5/14
CPC分类号： G11B20/1423 , H03M5/145
摘要： The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding the compute the parity information.
摘要翻译：所公开的技术提供了用于基于游程长度限制代码和纠错码来编码数据以提供码字的系统和方法。码字包括基于RLL码产生的RLL编码数据和基于纠错码产生的奇偶校验信息。奇偶校验信息在RLL编码数据之间进行交织。在一个实施例中，通过分别产生RLL编码数据和奇偶校验信息，以及在RLL编码数据之间交织奇偶校验信息来产生码字。在一个实施例中，通过产生RLL编码数据产生码字，并且使用擦除解码来计算奇偶校验信息。

9. 发明申请

WO2015047730A1 METHOD AND APPARATUS FOR DETERMINING POSITION OF MULTIPLE DRIVE HEADS 审中-公开
标题翻译：用于确定多个驱动头的位置的方法和装置
公开(公告)号：WO2015047730A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/054964
申请日：2014-09-10
申请人： MARVELL WORLD TRADE LTD. , OBERG, Mats , ZOU, Qiyue , BURD, Gregory
发明人： OBERG, Mats , ZOU, Qiyue , BURD, Gregory
IPC分类号： G11B5/596 , G11B5/48 , G11B5/55
CPC分类号： G11B5/59627 , G11B5/4886 , G11B5/553 , G11B5/59683
摘要： Determining the radial position of a first read head of a storage device includes reading servo data from a storage media platter surface using the first read head, deriving from that servo data a first position error signal representing a first estimate of the radial position of the first read head, reading the servo data from the storage media platter surface using a different read head, deriving from that servo data a second position error signal representing an estimate of the radial position of the different read head, and combining the first estimate of the radial position of the first read head and the estimate of the radial position of the different read head to obtain a revised estimate of the radial position of the first read head. The combining could include taking account of a known positional offset between the first read head and the different read head.
摘要翻译：确定存储设备的第一读取头的径向位置包括使用第一读取头从存储介质盘表面读取伺服数据，从该伺服数据中导出第一位置误差信号，该第一位置误差信号表示第一读取头的径向位置的第一估计读取头，使用不同的读取头从存储介质盘表面读取伺服数据，从该伺服数据导出表示不同读取头的径向位置的估计的第二位置误差信号，以及组合径向的第一估计第一读取头的位置和不同读取头的径向位置的估计，以获得第一读取头的径向位置的修正估计。组合可以包括考虑在第一读头和不同读头之间已知的位置偏移。

10. 发明申请

WO2015009718A1 SYSTEMS AND METHODS FOR CALIBRATING READ AND WRITE OPERATIONS IN TWO DIMENSIONAL MAGNETIC RECORDING 审中-公开
标题翻译：用于在两维磁记录中校准读取和写入操作的系统和方法
公开(公告)号：WO2015009718A1
公开(公告)日：2015-01-22
申请号：PCT/US2014/046690
申请日：2014-07-15
申请人： MARVELL WORLD TRADE LTD. , ZOU, Qiyue , MADDEN, Michael , BURD, Gregory
发明人： ZOU, Qiyue , MADDEN, Michael , BURD, Gregory
IPC分类号： G11B20/10
CPC分类号： G11B5/455 , G11B5/012 , G11B5/4886 , G11B5/58 , G11B5/59627 , G11B5/59683 , G11B20/10
摘要： Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric.
摘要翻译：提供了用于使用第一读取器和第二读取器校准从存储设备检索的信号的系统和方法。系统和方法还包括使用第一读取器读取第一信号和使用第二读取器读取第二信号。控制电路基于第一信号和第二信号的组合来计算与第一读取器和第二读取器相关联的校准度量。部分地基于所计算的校准度量，随后对第一信号和第二信号中的至少一个进行解码。

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