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1. 发明授权

US07920436B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US07920436B2
公开(公告)日：2011-04-05
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/00
CPC分类号： G11C7/062
摘要： A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

2. 发明申请

US20100149896A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20100149896A1
公开(公告)日：2010-06-17
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/06 , H03K5/24
CPC分类号： G11C7/062
摘要： A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

3. 发明申请

US20070047325A1 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US20070047325A1
公开(公告)日：2007-03-01
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

4. 发明授权

US06734701B2 Fast controlled output buffer 有权
标题翻译：快速控制输出缓冲器
公开(公告)号：US06734701B2
公开(公告)日：2004-05-11
申请号：US10323614
申请日：2002-12-18
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： H03K1716
CPC分类号： H03K17/166 , H03K17/165 , H03K19/00361
摘要： An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor feedback controlled by an output capacitor.
摘要翻译：输出缓冲器接通控制电路包括多个晶体管和放电电流控制电路。第一晶体管具有连接到内部电压线并由输出数据源控制的第一端子。第二晶体管具有连接到内部电压线的第一端子，并由第一晶体管的第二端子控制。第二晶体管还具有连接到输出电容器的第一端子的第二端子。第三晶体管由输出数据源控制，并具有连接到公共电压的第一端子。数字控制第四晶体管，并且具有连接到第二晶体管的第二端子的第一端子。第四晶体管还具有连接到公共电压的第二端子。放电电流控制电路优选地被主动地控制并且连接在第一晶体管的第二端子和第三晶体管的第二端子之间。放电电流控制电路优选地包括放电电阻器和由输出电容器控制的镜像电流晶体管反馈。

5. 发明申请

US20080170442A1 Column leakage compensation in a sensing circuit 有权
标题翻译：检测电路中的列泄漏补偿
公开(公告)号：US20080170442A1
公开(公告)日：2008-07-17
申请号：US11652828
申请日：2007-01-12
申请人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
发明人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

6. 发明申请

US20060114721A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20060114721A1
公开(公告)日：2006-06-01
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

7. 发明申请

US20080170454A1 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

8. 发明授权

US06794927B2 Modular charge pump architecture 有权
标题翻译：模块化电荷泵结构
公开(公告)号：US06794927B2
公开(公告)日：2004-09-21
申请号：US10328911
申请日：2002-12-24
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/077
摘要： An voltage regulation apparatus for generating a supply voltage internally within an integrated circuit with a modular arrangement of charge pumps. The charge pumps feature a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween. Each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node. Desired output voltages are obtained by using combinatorial clock signals, generated by a logic circuit, directed to the various charge pump stages.
摘要翻译：一种电压调节装置，用于在具有电荷泵的模块化布置的集成电路内部产生电源电压。电荷泵具有第一多个并联连接的电荷泵级的块，包括电荷泵级的第一级，电荷泵级的最后一级，以及其间的至少一个中间电荷泵级。电荷泵级的每个并联连接的块包括串联级联的第二组多个电荷泵级的组; 以及连接到输出节点的输出级。通过使用由逻辑电路产生的组合时钟信号来获得期望的输出电压，指向各种电荷泵级。

9. 发明申请

US20060085622A1 Method and system for managing address bits during buffered program operations in a memory device 有权
标题翻译：用于在存储器件中缓存的程序操作期间管理地址位的方法和系统
公开(公告)号：US20060085622A1
公开(公告)日：2006-04-20
申请号：US11123682
申请日：2005-05-06
申请人： Simone Bartoli , Stefano Surico , Davide Manfre , Donato Ferrario
发明人： Simone Bartoli , Stefano Surico , Davide Manfre , Donato Ferrario
IPC分类号： G06F12/10
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
摘要翻译：描述用于管理用于多个单词的缓冲程序操作的方法和系统。一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。每个词都存储在多个位置的位置。这些单词与位置的内部地址位相关联。至少一个内部地址位是与所有字对应的至少一个组地址位。内部地址位的剩余部分与至少一个字相关联。所述至少一个位位置存储所述字的至少一个组地址位。因此，在一个方面，该方法和系统包括将每个单词存储在缓冲器位置之一中。该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。

10. 发明授权

US07447071B2 Low voltage column decoder sharing a memory array p-well 有权
标题翻译：共享一个存储阵列p-well的低压列解码器
公开(公告)号：US07447071B2
公开(公告)日：2008-11-04
申请号：US11557627
申请日：2006-11-08
申请人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
发明人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
IPC分类号： G11C11/34
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
摘要翻译：多个存储器子阵列形成在p阱区域中。每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

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