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1. 发明授权

US06716709B1 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps 有权
标题翻译：形成有栅格或岛状注入掩模的晶体管，以形成减少的扩散深度区域，而无需额外的掩模和工艺步骤
公开(公告)号：US06716709B1
公开(公告)日：2004-04-06
申请号：US10335322
申请日：2002-12-31
申请人： Lily Springer , Jeff Smith , Sheldon Haynie , Joe R. Trogolo
发明人： Lily Springer , Jeff Smith , Sheldon Haynie , Joe R. Trogolo
IPC分类号： H01L21336
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/74 , H01L21/8249 , H01L29/0821 , H01L29/7322
摘要： A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
摘要翻译：提供了使用单个注入工艺形成具有不同深度的两个区域的方法。具有与其相关联的两个开口的掩模形成在半导体本体上，其中一个开口具有大于植入设计规则的尺寸，另一个开口的尺寸小于设计规则。通过注入掩模对半导体本体进行注入，产生两个不同的掺杂区域，其中与较大开口相关联的区域具有比与较小开口相关的区域更多的掺杂剂。随后的激活和热处理导致一个区域扩散比第二区域更大的量，从而导致形成为同时具有不同深度的两个区域。

2. 发明授权

US06869851B2 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps 有权
标题翻译：形成有栅格或岛状注入掩模的晶体管，以形成减少的扩散深度区域，而无需额外的掩模和工艺步骤
公开(公告)号：US06869851B2
公开(公告)日：2005-03-22
申请号：US10761438
申请日：2004-01-20
申请人： Joe R. Trogolo , Lily Springer , Jeff Smith , Sheldon Haynie
发明人： Joe R. Trogolo , Lily Springer , Jeff Smith , Sheldon Haynie
IPC分类号： H01L21/266 , H01L21/331 , H01L21/74 , H01L21/8249 , H01L29/08 , H01L29/732 , H01L21/336 , H01L21/8836
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/74 , H01L21/8249 , H01L29/0821 , H01L29/7322
摘要： A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
摘要翻译：提供了使用单个注入工艺形成具有不同深度的两个区域的方法。具有与其相关联的两个开口的掩模形成在半导体本体上，其中一个开口具有大于植入设计规则的尺寸，另一个开口的尺寸小于设计规则。通过注入掩模对半导体本体进行注入，产生两个不同的掺杂区域，其中与较大开口相关联的区域具有比与较小开口相关的区域更多的掺杂剂。随后的激活和热处理导致一个区域扩散比第二区域更大的量，从而导致形成为同时具有不同深度的两个区域。

3. 发明授权

US07615805B2 Versatile system for optimizing current gain in bipolar transistor structures 有权
标题翻译：用于优化双极晶体管结构中电流增益的通用系统
公开(公告)号：US07615805B2
公开(公告)日：2009-11-10
申请号：US11745906
申请日：2007-05-08
申请人： Joe R. Trogolo , Tathagata Chatterjee , Lily X. Springer , Jeffrey P. Smith
发明人： Joe R. Trogolo , Tathagata Chatterjee , Lily X. Springer , Jeffrey P. Smith
IPC分类号： H01L31/0328
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
摘要翻译：公开了用于设计双极发射器结构的电接触的装置和方法。确定发射极结构（106,306,404,404）的面积和电接触结构（108,308,402,406）所需的电流密度通过量。基于所需的电流密度确定所需的电接触面积，并且然后设计电接触结构以将所需的电接触面积相对于发射器结构区域最小化。

4. 发明申请

US20080026515A1 Silicide block isolated junction field effect transistor source, drain and gate 有权
标题翻译：硅化物阻隔隔离结场效应晶体管源极，漏极和栅极
公开(公告)号：US20080026515A1
公开(公告)日：2008-01-31
申请号：US11493229
申请日：2006-07-26
申请人： Badih El-Kareh , Hiroshi Yasuda , Scott Gerard Balster , Philipp Steinmann , Joe R. Trogolo
发明人： Badih El-Kareh , Hiroshi Yasuda , Scott Gerard Balster , Philipp Steinmann , Joe R. Trogolo
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译：结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。

5. 发明申请

US20090079446A1 Method to Accurately Estimate the Source and Drain Resistance of a MOSFET 有权
标题翻译：准确估计MOSFET的源极和漏极电阻的方法
公开(公告)号：US20090079446A1
公开(公告)日：2009-03-26
申请号：US11860993
申请日：2007-09-25
申请人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
发明人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.
摘要翻译： MOS晶体管的参数（也称为MOSFET）的参数（如阈值电位）的测量需要源极和漏极串联电阻的精确估计。在与MOSFET的连接包括显着的外部串联电阻的情况下，如在部分制造或去处理的探测晶体管中发生的那样，也需要外部电阻的精确估计。本发明包括一种用于估计MOSFET的串联电阻的方法，包括与MOSFET连接的电阻（例如探针触点）。该方法适用于可在源极，漏极，栅极和衬底端子上访问的任何MOSFET，并且不需要其他测试结构或特殊连接，例如开尔文连接。

6. 发明授权

US06856000B2 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies 有权
标题翻译：降低NPN晶体管中的1 / f噪声，而不降低集成电路技术中PNP晶体管的性能
公开(公告)号：US06856000B2
公开(公告)日：2005-02-15
申请号：US10266476
申请日：2002-10-08
申请人： Joe R. Trogolo , William Loftin , William F. Kyser, Jr.
发明人： Joe R. Trogolo , William Loftin , William F. Kyser, Jr.
IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/08 , H01L29/73
CPC分类号： H01L29/66287 , H01L21/82285 , H01L27/0826 , H01L29/0804
摘要： An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
摘要翻译：在NPN晶体管（280,220）和PNP晶体管（290,200）的发射极区域中形成界面氧化物层（185）。氟选择性地引入到NPN晶体管（220）的多晶硅发射极区域中，以降低NPN晶体管中的1 / f噪声。

7. 发明授权

US5034337A Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices 失效
标题翻译：制造集成了多外延功率晶体管与逻辑/模拟器件的集成电路的方法
公开(公告)号：US5034337A
公开(公告)日：1991-07-23
申请号：US576136
申请日：1990-08-29
申请人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
发明人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
IPC分类号： H01L21/74 , H01L21/8222 , H01L21/8226 , H01L21/8234 , H01L21/8248 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/74 , H01L21/8222 , H01L21/8226 , H01L21/8234 , H01L21/8248 , Y10S148/011
摘要： A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.
摘要翻译：制造涉及多个外延层生长步骤的半导体器件的工艺。

8. 发明授权

US07670890B2 Silicide block isolated junction field effect transistor source, drain and gate 有权
标题翻译：硅化物阻隔隔离结场效应晶体管源极，漏极和栅极
公开(公告)号：US07670890B2
公开(公告)日：2010-03-02
申请号：US11493229
申请日：2006-07-26
申请人： Badih El-Kareh , Hiroshi Yasuda , Scott Gerard Balster , Philipp Steinmann , Joe R. Trogolo
发明人： Badih El-Kareh , Hiroshi Yasuda , Scott Gerard Balster , Philipp Steinmann , Joe R. Trogolo
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译：结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。

9. 发明授权

US5455447A Vertical PNP transistor in merged bipolar/CMOS technology 失效
标题翻译：并联双极/ CMOS技术中的垂直PNP晶体管
公开(公告)号：US5455447A
公开(公告)日：1995-10-03
申请号：US954605
申请日：1992-09-30
申请人： Louis N. Hutter , Joe R. Trogolo
发明人： Louis N. Hutter , Joe R. Trogolo
IPC分类号： H01L27/06 , H01L29/732 , H01L29/72 , H01L27/10 , H01L27/15
CPC分类号： H01L29/7322 , H01L27/0623
摘要： A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in connection with the PMOS transistor (42).
摘要翻译：用于合并双极/ CMOS技术的垂直PNP结构具有作为集电极区的P +掩埋层（84），其通过N-掩埋层（82）与P衬底（48）隔离。 P +掩埋层（84）向下扩散到N埋层（82）中并向上扩散到P-外延层（52d）中并进入基极区（54c）。基极区域（54c）以与PMOS晶体管（42）的N阱区域（54b）和NPN晶体管（40）的收集区域（54a）相同的处理步骤形成。通过扩散到基极区域（54c）中，收集器（84）和发射极（64e）之间的宽度减小。发射极（64e）可以与PMOS晶体管（42）的源极和漏极区域结合形成。垂直PNP晶体管（46）通过由与NPN晶体管（40）中使用的N + DUF区域（50a）形成的N +区域（50c）形成的环形环与其它晶体管器件横向隔离，并且N + 区域（56b）与NPN晶体管（40）的N +集电极区（56a）结合形成。 N + DUF区（50b）也可以与PMOS晶体管（42）结合使用。

10. 发明授权

US5153697A Integrated circuit that combines multi-epitaxial power transistors with logic/analog devices, and a process to produce same 失效
标题翻译：将多外延功率晶体管与逻辑/模拟器件相结合的集成电路，以及生产相同的工艺
公开(公告)号：US5153697A
公开(公告)日：1992-10-06
申请号：US695821
申请日：1991-05-06
申请人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
发明人： Dan M. Mosher , Cornelia H. Blanton , Joe R. Trogolo , Larry Latham , David R. Cotton
IPC分类号： H01L21/74 , H01L21/8222 , H01L21/8226 , H01L21/8234 , H01L21/8248 , H01L21/8249
CPC分类号： H01L21/8222 , H01L21/74 , H01L21/8226 , H01L21/8234 , H01L21/8248 , H01L21/8249
摘要： An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.
摘要翻译：在基板上具有第一N型外延层的N型半导体晶片上形成集成电路，在第一N型外延层上形成P型外延层，在P型上形成第二N型外延层型外延层。还存在将P型外延区域和第二N型外延区域的表面分离成外延槽区域以形成双极和CMOS器件的多组P型隔离区，其组合高功率，低功率，逻辑，开关，模拟，高电流，低电流，数字和线性双极晶体管以及CMOS晶体管。将不同类型设备的特性组合成单个流程。

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