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1. 发明授权

US6048789A IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids 失效
标题翻译： IC连接形成与化学机械抛光和二氧化硅蚀刻与硝酸和氢氟酸溶液
公开(公告)号：US6048789A
公开(公告)日：2000-04-11
申请号：US807069
申请日：1997-02-27
申请人： Landon B. Vines , Craig A. Bellows , Walter D. Parmantie
发明人： Landon B. Vines , Craig A. Bellows , Walter D. Parmantie
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/02063 , H01L21/31053 , H01L21/31111 , Y10S438/906
摘要： An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.
摘要翻译：集成电路制造方法使用化学机械抛光（CMP）来平面化非平面亚金属（或金属间）二氧化硅介电层。平面化装置用氢氧化铵和柠檬酸水溶液清洗。使用硝酸和氢氟酸的混合物蚀刻暴露的水合二氧化硅，从CMP浆料中释放嵌入的污染物。氢氟酸是蚀刻剂，而硝酸与被除去的污染物结合以产生水溶性产物。因此，它们在水性漂洗液中携带，否则可能会再次污染该装置。通过形成接触孔，沉积金属和图案化金属，在蚀刻的氧化物上形成金属互连结构。该方法也可以应用于非平面的金属间电介质和随后的金属互连层。结果是具有更高产量和更可靠的制造集成电路的集成制造方法。

2. 发明授权

US5493132A Integrated circuit contact barrier formation with ion implant 失效
标题翻译：具有离子注入的集成电路接触屏障形成
公开(公告)号：US5493132A
公开(公告)日：1996-02-20
申请号：US394221
申请日：1995-02-24
申请人： Hunter B. Brugge , Kuang-Yeh Chang , Felix Fujishiro , Chang-Ou Lee , Walter D. Parmantie
发明人： Hunter B. Brugge , Kuang-Yeh Chang , Felix Fujishiro , Chang-Ou Lee , Walter D. Parmantie
IPC分类号： H01L21/285 , H01L21/768 , H01L33/00
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76859
摘要： A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.
摘要翻译：在CMOS结构的有源区域暴露之后溅射钛 - 钨阻挡层。穿过阻挡层并进入有源区域的离子注入破坏了阻挡层和下面的有效区域之间的边界。植入物可以包括氩或者替代地，硅。所得结构退火。沉积铝 - 铜合金的导体层。沉积TiW的抗反射涂层。然后将三层结构光刻图案化以限定接触和局部互连。退火之前的离子注入导致更小的接触电阻，这对于具有正掺杂有源区的势垒层边界是特别关键的。

3. 发明授权

US5793094A Methods for fabricating anti-fuse structures 失效
标题翻译：制造抗熔丝结构的方法
公开(公告)号：US5793094A
公开(公告)日：1998-08-11
申请号：US579780
申请日：1995-12-28
申请人： Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh , Walter D. Parmantie
发明人： Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh , Walter D. Parmantie
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.
摘要翻译：一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝用于接收金属二材料的沉积的层。该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成在金属一层和金属两层之间施加电压。所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。该方法还包括将金属二材料沉积到通孔中的步骤。

4. 发明授权

US5395773A MOSFET with gate-penetrating halo implant 失效
标题翻译：具有栅极穿透晕轮植入物的MOSFET
公开(公告)号：US5395773A
公开(公告)日：1995-03-07
申请号：US221338
申请日：1994-03-31
申请人： K. S. Ravindhran , Yu P. Han , Ravi Jhota , Walter D. Parmantie
发明人： K. S. Ravindhran , Yu P. Han , Ravi Jhota , Walter D. Parmantie
IPC分类号： H01L21/336 , H01L21/8238 , G01N33/24
CPC分类号： H01L29/6659 , H01L21/823807
摘要： After gates are patterned in a submicron CMOS process, a halo implant is performed with sufficient energy that the halo implant penetrates the gate structures to below the transistor channel regions. Where the substrate is not masked by gate materal, the halo implant penetrates below drain and source regions. During diffusion, this halo limits lateral diffusion of the source/drain dopants. The resulting transistor exhibits enhanced breakdown voltage characteristics during both on and off conditions.
摘要翻译：在亚微米CMOS工艺中对栅极进行构图之后，以足够的能量进行光晕注入，使得卤素注入器将栅极结构穿透到晶体管沟道区域的下方。在衬底不被栅极掩蔽的情况下，卤素植入物渗透在漏极和源极区域之下。在扩散期间，该晕圈限制了源极/漏极掺杂剂的横向扩散。所得到的晶体管在打开和关闭条件期间表现出增强的击穿电压特性。

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