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1. 发明授权

US4521848A Intersystem fault detection and bus cycle completion logic system 失效
标题翻译：系统故障检测和总线循环完成逻辑系统
公开(公告)号：US4521848A
公开(公告)日：1985-06-04
申请号：US296931
申请日：1981-08-27
申请人： Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
发明人： Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
IPC分类号： G06F13/36 , G06F13/40 , G06F3/04 , G06F9/46
CPC分类号： G06F13/4027 , G06F13/36 , G06F13/404
摘要： An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.
摘要翻译：公开了一种错误检测系统，其不仅指示但是消除了在数据处理系统中的通信总线之间的信息传送期间可能发生的某些错误，其中多个通信总线各自提供公共信息路径到包括存储器单元的多个数据处理单元控制单元，中央处理单元和ISL单元，并且其中多个通信总线中的每一个与ISL单元电连接，并且ISL单元成对地电连接。错误检测系统在任何通信总线上不需要任何数据处理单元的特殊支持软件或固件。

2. 发明授权

US4384322A Asynchronous multi-communication bus sequence 失效
标题翻译：异步多通道总线序列
公开(公告)号：US4384322A
公开(公告)日：1983-05-17
申请号：US109910
申请日：1980-01-07
申请人： Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
发明人： Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
IPC分类号： G06F13/36 , G06F13/40 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/404 , G06F13/4045
摘要： An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.
摘要翻译：提供了一种系统间链路（ISL）单元中的系统间通信控制系统，以适应在数据处理系统中的通信总线之间的二进制编码信息的同时双向传送，其中多个通信总线通过ISL单元双向电互连，并且信息可以在多个通信总线之间异步传输。

3. 发明授权

US4236208A Test mode control logic system 失效
标题翻译：测试模式控制逻辑系统
公开(公告)号：US4236208A
公开(公告)日：1980-11-25
申请号：US956384
申请日：1978-10-31
申请人： David B. O'Keefe , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
发明人： David B. O'Keefe , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
IPC分类号： G06F11/27 , G06F13/40 , G06F13/42 , G06F3/04 , G06F11/22
CPC分类号： G06F13/4213 , G06F11/27 , G06F13/4027
摘要： A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus. The remote ISL unit is effectively non-existent to other data processing units on the remote bus.
摘要翻译：公开了用于验证在数据处理系统中电连接本地和远程通信总线的本地和远程系统间链路（ISL）单元中的存储器和非存储器数据和控制路径的可操作性的逻辑控制系统。数据处理系统可以包括两个或更多个通过双ISL单元电连接的通信总线。控制逻辑架构适应于从本地总线上的CPU接收测试模式命令以启动测试模式操作，其中本地和远程ISL单元的存储器和非存储器数据以及控制路径被切换，线路和从本地总线接收的二进制编码信息通过ISL单元传递到远程总线上，并返回到本地总线存储器资源进行验证。没有使用或影响远程总线资源，远程ISL单元将忽略从远程总线上任何其他数据处理单元接收到的任何通信。远程ISL单元实际上不存在于远程总线上的其他数据处理单元。

4. 发明授权

US4384327A Intersystem cycle control logic 失效
标题翻译：系统周期控制逻辑
公开(公告)号：US4384327A
公开(公告)日：1983-05-17
申请号：US223540
申请日：1981-01-08
申请人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
发明人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F9/46 , G06F3/04
CPC分类号： G06F13/4045 , G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑控制系统，其中可以在多个通信总线之间传送信息，同时在每个通信总线上继续进行信息流总线速率和通信总线之间的附加信息传输继续由ISL单元处理。

5. 发明授权

US4231086A Multiple CPU control system 失效
标题翻译：多CPU控制系统
公开(公告)号：US4231086A
公开(公告)日：1980-10-28
申请号：US956382
申请日：1978-10-31
申请人： Bruce H. Tarbox , Kenneth E. Bruce , John W. Conway , Ralph M. Lombardo, Jr.
发明人： Bruce H. Tarbox , Kenneth E. Bruce , John W. Conway , Ralph M. Lombardo, Jr.
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F9/46 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses.The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.
摘要翻译：提供了系统间链路（ISL）单元中的逻辑系统，用于避免数据处理系统中可能发生的死锁状况，其中一个通信总线上的多个CPU尝试与远程通信总线上的资源进行通信。数据处理系统具有多个通信总线，每个通信总线为包括存储单元，外围控制单元，中央处理单元（CPU）和ISL单元的多个数据处理单元提供公共信息路径，并且多个通信总线中的每一个与 ISL单元和ISL单元成对电连接。

6. 发明授权

US4433376A Intersystem translation logic system 失效
标题翻译：系统翻译逻辑系统
公开(公告)号：US4433376A
公开(公告)日：1984-02-21
申请号：US216600
申请日：1980-12-15
申请人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.
摘要翻译：提供了一种用于容纳数据处理系统的两个或更多个通信总线之间的信息交换的逻辑系统，其中独立通信总线上的多个中央处理单元和多个存储器单元可以具有相同的逻辑地址。存储器和CPU地址通过多个灵活的地址转换范围以总线速率转换，以使得一个通信总线上的数据处理单元能够访问包含所有通信总线上的所有数据处理单元的明显的连续的地址范围。

7. 发明授权

US4370708A Logic system for selectively reconfiguring an intersystem communication link 失效
标题翻译：用于选择性地重新配置系统间通信链路的逻辑系统
公开(公告)号：US4370708A
公开(公告)日：1983-01-25
申请号：US110000
申请日：1980-01-07
申请人： Kenneth E. Bruce , John W. Conway , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
发明人： Kenneth E. Bruce , John W. Conway , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
IPC分类号： G06F12/02 , G06F13/36 , G06F13/40 , G06F3/04
CPC分类号： G06F13/404 , G06F12/0284 , G06F13/36 , G06F13/4027 , G06F13/4045
摘要： A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传送的系统间链路（ISL）单元中的逻辑控制系统，其中可以重新配置ISL单元以重新分配通信总线资源，而不会引起过多的软件开销时间损失。

8. 发明授权

US4236209A Intersystem transaction identification logic 失效
标题翻译：系统事务识别逻辑
公开(公告)号：US4236209A
公开(公告)日：1980-11-25
申请号：US956389
申请日：1978-10-31
申请人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04 , G06F13/00
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑系统，其中文件寄存器中的专用位置响应于从本地通讯总线。识别出响应于总线周期请求发起的ISL事务。 ISL事务被并行处理，并且内存传输与非内存传输隔离，以避免内存传输中不必要的延迟。

9. 发明授权

US4234919A Intersystem communication link 失效
标题翻译：系统间通信链路
公开(公告)号：US4234919A
公开(公告)日：1980-11-18
申请号：US956385
申请日：1978-10-31
申请人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
发明人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.
摘要翻译：被称为系统间链路单元（ISL）的逻辑系统被提供用于在数据处理系统中的两个或多个通信总线之间容纳二进制编码信息的传送，其中包括存储器和非存储器读写请求的信息，CPU到 CPU中断，外围控制单元到CPU中断可以在多个通信总线之间传送，每个通信总线支持包括多个CPU的多个数据处理单元，而不会显着影响各个通信总线的总线速率。来自通信总线的二进制编码信息被异步地获取，并且并行地容纳不同类型的多个总线通信。还可以动态地重新配置ISL单元以提供通信总线之间的通信总线资源的重新分配。

10. 发明授权

US5134706A Bus interface interrupt apparatus 失效
标题翻译：总线接口中断设备
公开(公告)号：US5134706A
公开(公告)日：1992-07-28
申请号：US511873
申请日：1990-04-19
申请人： David E. Cushing , Ralph M. Lombardo, Jr. , Forrest M. Phillips
发明人： David E. Cushing , Ralph M. Lombardo, Jr. , Forrest M. Phillips
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged. Using this information circuits in the bus interface interrupt arrangement are operated to pass data and addresses between the primary bus and the chosen bus. These circuits are operated in a manner to pass data between busses having different data path sizes.
摘要翻译：公开了一种总线接口中断装置，其为多总线计算机系统中的每个总线提供单独的中断控制器，其中处理器连接到总线中的一个。与处理器连接的主总线以外的每个总线决定的中断请求与连接到主总线的电路的中断一起输入到主总线的中断控制器。中断控制器为主总线决定的中断请求连接到处理器的中断输入。所有中断控制器连接到主总线，并可由处理器访问。当处理器选择来自其他总线以外的总线的中断时，处理器必须读取中断控制器以首先确定哪个总线，然后识别产生已被确认的中断的电路。在总线接口中断布置中使用这些信息电路可以在主总线和所选总线之间传递数据和地址。这些电路的操作方式是在具有不同数据路径尺寸的总线之间传递数据。

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