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1. 发明申请

US20130146959A1 Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors 有权
标题翻译：用ETSOI晶体管形成片上高品质电容器的方法和结构
公开(公告)号：US20130146959A1
公开(公告)日：2013-06-13
申请号：US13316635
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/0629 , H01L27/105 , H01L27/10805 , H01L28/40 , H01L29/66181 , H01L29/94
摘要： An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中通过ETSOI和薄BOX层蚀刻，分别在其晶体管和电容器区域中形成ETSOI晶体管和电容器。电容器形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器或变容二极管。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

2. 发明授权

US08338260B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08338260B2
公开(公告)日：2012-12-25
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

3. 发明申请

US20110254090A1 RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权
标题翻译：从应力衬里增强应变耦合的提高源/排水结构
公开(公告)号：US20110254090A1
公开(公告)日：2011-10-20
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

4. 发明授权

US08853038B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08853038B2
公开(公告)日：2014-10-07
申请号：US13614572
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336 , H01L29/66 , H01L29/786 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译：栅极堆叠形成在掩埋氧化物层上方的硅层上。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。在硅层和栅叠层上形成第一氮化物层。在第一氮化物层上形成氧化物层。在氧化物层上形成第二氮化物层。蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。

5. 发明授权

US08890245B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08890245B2
公开(公告)日：2014-11-18
申请号：US13570833
申请日：2012-08-09
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

6. 发明授权

US08617937B2 Forming narrow fins for finFET devices using asymmetrically spaced mandrels 有权
标题翻译：使用不对称间隔的心轴形成finFET器件的窄鳍
公开(公告)号：US08617937B2
公开(公告)日：2013-12-31
申请号：US12886850
申请日：2010-09-21
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L29/66795 , H01L21/845
摘要： A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的鳍片的方法包括在半导体衬底上形成多个牺牲心轴。多个牺牲心轴沿着第一方向彼此间隔开第一距离，并且沿第二方向间隔开第二距离。间隔层形成在牺牲心轴的侧壁上，使得沿着第一方向的牺牲心轴之间的间隔层的部分被合并在一起。沿着第二方向的牺牲心轴之间的间隔层的部分保持间隔开。牺牲心轴被去除。对应于间隔层的图案被转移到半导体层中以形成多个半导体鳍片。相邻的翅片对在与合并的间隔层相对应的位置处彼此合并。

7. 发明申请

US20120061759A1 Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
公开(公告)号：US20120061759A1
公开(公告)日：2012-03-15
申请号：US12882490
申请日：2010-09-15
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/782
CPC分类号： H01L29/78654 , H01L29/66628 , H01L29/66772
摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
摘要翻译：在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。还提供了形成上述MOSFET器件的方法。

8. 发明申请

US20120193713A1 FinFET device having reduce capacitance, access resistance, and contact resistance 有权
标题翻译： FinFET器件具有降低电容，访问电阻和接触电阻
公开(公告)号：US20120193713A1
公开(公告)日：2012-08-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译：形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。提供掩埋氧化物，鳍状物，栅极和第一间隔物。该鳍被掺杂以形成在栅极下方延伸的延伸结。第二间隔件形成在延伸接头的顶部。每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

9. 发明授权

US08748258B2 Method and structure for forming on-chip high quality capacitors with ETSOI transistors 有权
标题翻译：用ETSOI晶体管形成片上高品质电容器的方法和结构
公开(公告)号：US08748258B2
公开(公告)日：2014-06-10
申请号：US13316635
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0629 , H01L27/105 , H01L27/10805 , H01L28/40 , H01L29/66181 , H01L29/94
摘要： An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中通过ETSOI和薄BOX层蚀刻，分别在其晶体管和电容器区域中形成ETSOI晶体管和电容器。电容器形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器或变容二极管。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

10. 发明授权

US08900936B2 FinFET device having reduce capacitance, access resistance, and contact resistance 有权
标题翻译： FinFET器件具有降低电容，访问电阻和接触电阻
公开(公告)号：US08900936B2
公开(公告)日：2014-12-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译：形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。提供掩埋氧化物，鳍状物，栅极和第一间隔物。该鳍被掺杂以形成在栅极下方延伸的延伸结。第二间隔件形成在延伸接头的顶部。每个第二间隔件邻近门的任一侧的第一间隔件之一。延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

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