专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08592270B2 Non-relaxed embedded stressors with solid source extension regions in CMOS devices 失效
标题翻译： CMOS器件中具有固态源延伸区域的非轻松嵌入式应力源
公开(公告)号：US08592270B2
公开(公告)日：2013-11-26
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, Jr.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

2. 发明申请

US20120302019A1 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
标题翻译： CMOS器件中固体源扩展区非松弛嵌入式压电器
公开(公告)号：US20120302019A1
公开(公告)日：2012-11-29
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

3. 发明申请

US20130299897A1 INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN 有权
公开(公告)号：US20130299897A1
公开(公告)日：2013-11-14
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

4. 发明授权

US09219129B2 Inverted thin channel mosfet with self-aligned expanded source/drain 有权
标题翻译：反向薄沟道MOSFET，具有自对准扩展源极/漏极
公开(公告)号：US09219129B2
公开(公告)日：2015-12-22
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, Jr.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, Jr.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L21/74 , H01L27/12
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A semiconductor structure including expanded source/drain regions that extend in an opposite direction of a gate electrode is provided. The semiconductor structure includes a stack of a body-containing region and a buried insulator portion, a gate dielectric in contact with a surface of the body-containing region, a gate electrode in contact with the gate dielectric, and a source region and a drain region laterally spaced by, and in contact with, the stack. The semiconductor structure further includes a contact level dielectric layer deposited on surfaces of the source region, the drain region and the buried insulator portion.
摘要翻译：提供包括在栅电极的相反方向上延伸的扩展的源极/漏极区域的半导体结构。所述半导体结构包括：体内区域和掩埋绝缘体部分的堆叠体，与所述主体容纳区域的表面接触的栅极电介质，与所述栅极电介质接触的栅极电极，以及源极区域和漏极横向间隔开并与堆叠接触的区域。半导体结构还包括沉积在源极区域，漏极区域和埋入绝缘体部分的表面上的接触电介质层。

5. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

6. 发明授权

US08803233B2 Junctionless transistor 有权
标题翻译：无结晶体晶体管
公开(公告)号：US08803233B2
公开(公告)日：2014-08-12
申请号：US13242861
申请日：2011-09-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
摘要翻译：晶体管包括半导体层，并且在半导体层上形成栅极电介质。栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。该渐变掺杂剂区域的掺杂浓度逐渐降低。晶体管还包括与有源区相邻的源区和漏区。源极和漏极区域和有源区域具有相同的导电类型。

7. 发明授权

US08564040B1 Inversion mode varactor 有权
标题翻译：反转模式变容二极管
公开(公告)号：US08564040B1
公开(公告)日：2013-10-22
申请号：US13570360
申请日：2012-08-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层，其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

8. 发明申请

US20130207189A1 INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME 有权
标题翻译：具有降低硅氧烷接触电阻的上升源排水装置的集成电路及其制造方法
公开(公告)号：US20130207189A1
公开(公告)日：2013-08-15
申请号：US13852103
申请日：2013-03-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

9. 发明授权

US08318574B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

10. 发明申请

US20120261757A1 STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权
标题翻译：具有单个间距的垂直源/源压应力的应变薄体CMOS器件
公开(公告)号：US20120261757A1
公开(公告)日：2012-10-18
申请号：US13531053
申请日：2012-06-22
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式