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1. 发明授权

US06969645B2 Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells 失效
标题翻译：包括具有存储单元的非易失性存储器的半导体器件的制造方法
公开(公告)号：US06969645B2
公开(公告)日：2005-11-29
申请号：US10482185
申请日：2002-07-03
申请人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
发明人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28273 , H01L29/42328
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T1) with a select gate (1) and including a memory transistor (T2) with a floating gate (2) and a control gate (3). In a semiconductor body (10), active semiconductor regions are formed which are mutually insulated by field oxide regions (12). Next, the surface (11) is provided with a gate oxide layer (14) and a first layer of a conductive material wherein the select gate (1) is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (17). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (18). Next, a second layer of a conductive material (21), an interlayer dielectric (25) and a third layer of a conductive material (26) are deposited. The control gate (3) extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate (2) is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.
摘要翻译：一种制造包括非易失性存储器的半导体器件的方法，所述非易失性存储器具有包括具有选择栅极（1）并且包括具有浮置栅极（2）的存储晶体管（T 2）的选择晶体管（T 1）的存储器单元（Mij）和控制门（3）。在半导体本体（10）中，形成由场氧化物区域（12）相互绝缘的有源半导体区域。接下来，表面（11）设置有栅极氧化物层（14）和其中蚀刻选择栅极（1）的导电材料的第一层。随后，垂直于表面延伸的选择栅的壁设置有隔离材料（17）。选择栅极旁边的栅极氧化层被隧道氧化物层（18）代替。接下来，沉积第二层导电材料（21），层间电介质（25）和第三层导电材料（26）。在第三层中形成在选择栅极上方和下方延伸的控制栅极（3）。使用控制栅极作为掩模，随后在第二层导电材料中蚀刻浮栅（2）。在该方法中，第二层被沉积成比选择栅极更大的厚度，然后在沉积层间电介质和第三层导电材料之前将该层平坦化。以这种方式，可以制造紧凑的存储单元。

2. 发明授权

US06472706B2 Semiconductor device 有权
公开(公告)号：US06472706B2
公开(公告)日：2002-10-29
申请号：US09902920
申请日：2001-07-11
申请人： Franciscus Petrus Widdershoven , Jurriaan Schmitz
发明人： Franciscus Petrus Widdershoven , Jurriaan Schmitz
IPC分类号： H01L2972
CPC分类号： H01L27/11568 , H01L29/792
摘要： A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

3. 发明申请

US20050029572A1 Fabrication of non-volatile memory cell 审中-公开
标题翻译：非易失性存储单元的制造
公开(公告)号：US20050029572A1
公开(公告)日：2005-02-10
申请号：US10499395
申请日：2002-12-20
申请人： Jurriaan Schmitz
发明人： Jurriaan Schmitz
IPC分类号： H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114
摘要： Fabrication of a semiconductor device comprising a compact cellon a semiconductor substrate (3) including at least two adjacent elements separated by a spacing, the elements being defined from a layer stack that includes an isolation layer(4) on the substrate (3) and a poly-Si layer (5) on the isolation layer (4), wherein the fabrication includes:—depositing on the layer stack a mask (M1; M3) including at least one vertical isolation layer (10), a first (9) and a second (11) silicon nitride layer, the vertical isolation layer (10) separating the first (9) and second (11) silicon nitride layers and being located where the spacing is to be formed;—performing a first selective etch on the vertical isolation layer (10) to form a narrow slit (A);—performing a stack etch including a first stack etch process for selectively etching the poly-Si layer (5), using thenarrow slit (A) to define the location for the first stack etch process and the spacing between the elements.
摘要翻译：包括紧密蜂窝半导体器件的半导体器件的制造，所述半导体衬底（3）包括由间隔隔开的至少两个相邻元件，所述元件由层叠体限定，所述层叠层包括在所述衬底（3）上的隔离层（4）在所述隔离层（4）上的多晶硅层（5），其中所述制造包括： - 在所述层堆叠上沉积包括至少一个垂直隔离层（10），第一（9）和第二（11）氮化硅层，所述垂直隔离层（10）分离所述第一（9）和第二（11）氮化硅层，并且位于要形成间隔的位置; - 在垂直方向上执行第一选择性蚀刻隔离层（10）以形成窄缝（A）; - 执行堆叠蚀刻，其包括用于选择性地蚀刻所述多晶硅层（5）的第一堆叠蚀刻工艺，使用所述狭缝（A）来限定所述第一堆栈蚀刻过程和元素之间的间距。

4. 发明授权

US06255183B1 Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers 失效
标题翻译：具有使用SiGe间隔物的具有LDD结构的MOS晶体管的半导体器件的制造
公开(公告)号：US06255183B1
公开(公告)日：2001-07-03
申请号：US09064207
申请日：1998-04-22
申请人： Jurriaan Schmitz , Youri V. Ponomarev , Pierre H. Woerlee
发明人： Jurriaan Schmitz , Youri V. Ponomarev , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/28247 , H01L21/823864 , H01L29/665 , Y10S438/923
摘要： A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si1-xGex, 0.1
摘要翻译：一种制造具有LDD结构的MOS晶体管的半导体器件的方法。在硅衬底（1）的表面（5）上形成栅电介质（6）和栅电极（7,8）。然后暴露与栅电极相邻的表面，并且在与栅电极相邻的表面的边缘（9）上形成一层半导体材料（10）。随后，栅极电极和半导体材料层用作掩模，随后引入离子（13,14）。最后，进行热处理，由此通过激活注入的离子并且通过从半导体材料层扩散掺杂剂的原子而形成源极区（16,17）和漏极区（18,19）。这些由扩散形成的这些区域的部分（b）在这里是弱掺杂的，位于通过激活注入的离子和沟道区（20,21）形成的更强的掺杂部分（a）之间。因此形成了LDD结构。在该方法中，在与栅电极相邻的边缘上设置由Si1-xGex形成的半导体材料层，0.1

5. 发明授权

US07262460B2 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US07262460B2
公开(公告)日：2007-08-28
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond J. E. Hueting , Erwin A. Hijzen , Andreas H. Montree , Michael A. A. In't Zandt , Gerrit E. J. Koops
发明人： Jurriaan Schmitz , Raymond J. E. Hueting , Erwin A. Hijzen , Andreas H. Montree , Michael A. A. In't Zandt , Gerrit E. J. Koops
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

6. 发明授权

US06403426B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06403426B1
公开(公告)日：2002-06-11
申请号：US09527202
申请日：2000-03-16
申请人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
发明人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1045 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface 2 of the semiconductor body 1, and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. In a next step, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess 15 in the dielectric layer 14 at the area of the planned gate. Then, impurities are introduced via the recess 15 into the channel region 13 of the semiconductor body 1 in a self-registered way by using the dielectric layer 14, as a mask and an insulating layer is applied, forming the gate dielectric, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.
摘要翻译：在制造半导体器件的方法中，该半导体器件包括晶体管，该晶体管具有通过栅极电介质在半导体本体的表面处与沟道区绝缘的栅极，在半导体本体的表面2处限定第一导电类型的有源区域4 1，并且施加由耐火材料组成的图案层，该图案层限定了将在该工艺的稍后阶段提供的规划浇口的区域，并且在形成源区11和排水区期间用作掩模在下一步骤中，提供电介质层14，其厚度足够大以覆盖图案化层，该电介质层14通过部分厚度被去除其厚度的一部分，借助于直到图案化层被暴露之前的材料去除处理，去除图案层，从而在计划的栅极的区域处在电介质层14中形成凹陷15。然后，通过使用电介质层14作为掩模，并且施加绝缘层，通过凹部15将杂质以自我注册的方式引入半导体本体1的沟道区域13中，形成栅极电介质，绝缘施加导电层，从而填充凹部，该导电层被成形为晶体管的栅极。

7. 发明授权

US06251729B1 Method of manufacturing a nonvolatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US06251729B1
公开(公告)日：2001-06-26
申请号：US09464004
申请日：1999-12-15
申请人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
发明人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11539 , H01L29/66545
摘要： In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.
摘要翻译：在半导体本体的表面上制造包括场效晶体管和非易失性存储元件的半导体器件的方法中，第一导电类型的第一和第二有源区限定在半导体本体的表面分别用于晶体管和存储器元件。半导体本体的表面随后涂覆有提供晶体管的牺牲栅极电介质和存储元件的浮置栅极电介质的第一绝缘层，该第一绝缘层然后被含硅层覆盖，所述含硅层提供牺牲栅极晶体管和存储元件的浮动栅极。在形成牺牲栅极和浮置栅极之后，晶体管和存储元件设置有第二导电类型的源区和漏区。在下一步骤中，施加电介质层，其通过材料去除处理至少部分其厚度去除，直到在第一和第二有源区域处的含硅层被暴露，然后将硅除去第一有源区，从而在电介质层中形成凹部。随后，在第二有源区施加第二绝缘层，提供存储元件的栅极间电介质，并且在提供晶体管的栅极电介质的第一有源区施加第三绝缘层。在形成栅极电介质和栅极间电介质之后，施加导电层，该导电层在第一有源区域被成形为晶体管的栅极，并且在第二有源区域处形成存储元件的控制栅极。

8. 发明授权

US06177303B1 Method of manufacturing a semiconductor device with a field effect transistor 有权
标题翻译：制造具有场效应晶体管的半导体器件的方法
公开(公告)号：US06177303B1
公开(公告)日：2001-01-23
申请号：US09379959
申请日：1999-08-24
申请人： Jurriaan Schmitz , Pierre H. Woerlee , Andreas H. Montree
发明人： Jurriaan Schmitz , Pierre H. Woerlee , Andreas H. Montree
IPC分类号： H01L21337
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/495 , H01L29/66545
摘要： In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).
摘要翻译：在已知的替代栅极工艺中，通过沉积厚的氧化物层，然后通过CMP平坦化该层，直到达到栅极，该相对高欧姆的多晶硅栅极被低欧姆金属栅极代替，该栅极可被选择性地去除和替换由金属门。通过将栅极结构设置为多晶硅栅极顶部的虚设多晶硅栅极（4）和氮化物层（5）的叠层，可大大简化工艺。当在CMP期间达到氮化物层时，停止CMP，从而排除对聚合物的攻击。相对于氧化物层（10）选择性地去除氮化物和多晶硅。

9. 发明授权

US08848194B2 Integrated plasmonic nanocavity sensing device 有权
标题翻译：集成等离子体纳米腔感测装置
公开(公告)号：US08848194B2
公开(公告)日：2014-09-30
申请号：US13639716
申请日：2011-04-06
申请人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
发明人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
IPC分类号： G01N21/55 , G01N21/64 , H01L31/12 , B82Y20/00 , G02B6/122 , G01N21/77 , B01L3/00
CPC分类号： G01N21/55 , B01L3/502715 , B01L2300/0654 , B01L2300/0663 , B82Y20/00 , G01N21/554 , G01N21/6454 , G01N21/648 , G01N21/6489 , G01N21/7746 , G01N2021/7776 , G01N2021/7786 , G01N2021/7789 , G02B6/1226 , H01L31/125
摘要： An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.
摘要翻译：描述了集成等离子体激元感测装置，其中集成装置包括：至少一个光源，包括第一导电层和第二导电层，以及在所述第一和第二导电层的至少一部分之间的光学有源层; 至少一个延伸穿过所述第一和第二导电层和所述光学有源层的纳米腔，其中所述光源被配置为产生适于光学激活所述纳米腔中的一个或多个谐振的表面等离子体模式; 以及至少一个光学检测器，其包括在所述纳米腔谐振器附近形成在所述衬底中的至少一个检测区域，其中所述光学检测器被配置为感测所述纳米腔中的光学激活的共振。

10. 发明申请

US20060049453A1 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US20060049453A1
公开(公告)日：2006-03-09
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
发明人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

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