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1. 发明授权

US07615926B2 Low voltage microcavity plasma device and addressable arrays 有权
标题翻译：低电压微腔等离子体器件和可寻址阵列
公开(公告)号：US07615926B2
公开(公告)日：2009-11-10
申请号：US11811892
申请日：2007-06-12
申请人： J. Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
IPC分类号： H01J17/49
CPC分类号： H01J11/12
摘要： Microcavity plasma devices and arrays of microcavity plasma devices are provided that have a reduced excitation voltage. A trigger electrode disposed proximate to a microcavity reduce the excitation voltage required between first and second electrodes to ignite a plasma in the microcavity when gas(es) or vapor(s) (or combinations thereof) are contained within the microcavity. The invention also provides symmetrical microplasma devices and arrays of microcavity plasma devices for which current waveforms are the same for each half-cycle of the voltage driving waveform. Additionally, the invention also provides devices that have standoff portions and voids that can reduce cross talk. The devices are preferably also used with a trigger electrode.
摘要翻译：提供微腔等离子体器件和微腔等离子体器件的阵列，其具有降低的激发电压。在微腔内包含气体或蒸汽（或其组合）时，靠近微腔设置的触发电极减小了第一和第二电极之间所需的激发电压，以点燃微腔中的等离子体。本发明还提供对称的微等离子体装置和微腔等离子体装置的阵列，其电流波形对于电压驱动波形的每个半周期是相同的。此外，本发明还提供了具有能够减少串扰的间隔部分和空隙的装置。这些装置优选地也与触发电极一起使用。

2. 发明申请

US20080129185A1 Low voltage microcavity plasma device and addressable arrays 有权
标题翻译：低电压微腔等离子体器件和可寻址阵列
公开(公告)号：US20080129185A1
公开(公告)日：2008-06-05
申请号：US11811892
申请日：2007-06-12
申请人： J.Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
发明人： J.Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
IPC分类号： H05H1/24
CPC分类号： H01J11/12
摘要： Microcavity plasma devices and arrays of microcavity plasma devices are provided that have a reduced excitation voltage. A trigger electrode disposed proximate to a microcavity reduce the excitation voltage required between first and second electrodes to ignite a plasma in the microcavity when gas(es) or vapor(s) (or combinations thereof) are contained within the microcavity. The invention also provides symmetrical microplasma devices and arrays of microcavity plasma devices for which current waveforms are the same for each half-cycle of the voltage driving waveform. Additionally, the invention also provides devices that have standoff portions and voids that can reduce cross talk. The devices are preferably also used with a trigger electrode.
摘要翻译：提供微腔等离子体器件和微腔等离子体器件的阵列，其具有降低的激发电压。在微腔内包含气体或蒸汽（或其组合）时，靠近微腔设置的触发电极减小了第一和第二电极之间所需的激发电压，以点燃微腔中的等离子体。本发明还提供对称的微等离子体装置和微腔等离子体装置的阵列，其电流波形对于电压驱动波形的每个半周期是相同的。此外，本发明还提供了具有能够减少串扰的间隔部分和空隙的装置。这些装置优选地也与触发电极一起使用。

3. 发明申请

US20130071297A1 ARRAYS OF METAL AND METAL OXIDE MICROPLASMA DEVICES WITH DEFECT FREE OXIDE 有权
标题翻译：金属和金属氧化物微孔器件与无氧氧化物的阵列
公开(公告)号：US20130071297A1
公开(公告)日：2013-03-21
申请号：US13527842
申请日：2012-06-20
申请人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
发明人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
IPC分类号： H01J37/32 , C25D11/02
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/00842 , B01J2219/00853 , B01J2219/00891 , C01B13/115 , C25D11/02 , C25D11/022 , C25D11/026 , C25D11/12 , C25D11/18 , C25D11/26 , H01J11/18 , H01J11/22 , H01J11/34 , H01J17/066 , H01J17/16 , H01J37/32055 , H05H2001/2412 , H05H2001/2418
摘要： A microplasma device includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel. At least one of the electrodes is encapsulated within the thick metal oxide layer. A method of fabricating a microcavity or microchannel plasma device includes anodizing a flat or gently curved or gently sloped metal substrate to form a thick layer of metal oxide consisting essentially of nanopores that are perpendicular to the surface of the metal substrate. Material removal is conducted to remove metal oxide material to form a microcavity or microchannel in the thick layer of metal oxide.
摘要翻译：微型装置包括至少部分地在基本上由无缺陷氧化物组成的厚金属氧化物层内限定的微腔或微通道。电极相对于微腔或微通道布置以刺激所述微腔或微通道中的血浆产生。至少一个电极被封装在厚的金属氧化物层内。一种制造微腔或微通道等离子体装置的方法包括阳极氧化平坦或轻柔地弯曲或缓慢倾斜的金属基底，以形成基本上由纳米孔组成的厚层，金属氧化物垂直于金属基底的表面。进行材料去除以除去金属氧化物材料以在金属氧化物的厚层中形成微腔或微通道。

4. 发明申请

US20100072893A1 ELLIPSOIDAL MICROCAVITY PLASMA DEVICES AND POWDER BLASTING FORMATION 有权
标题翻译： ELLIPSOIDAL微波等离子体装置和粉末喷砂形成
公开(公告)号：US20100072893A1
公开(公告)日：2010-03-25
申请号：US12235796
申请日：2008-09-23
申请人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
IPC分类号： H01J17/49 , H01J9/24
CPC分类号： H01J65/046 , H01J9/241 , H01J11/18
摘要： The invention provides microcavity plasma devices and arrays that are formed in layers that also seal the plasma medium, i.e., gas(es) and/or vapors. No separate packaging layers are required and additional packaging can be omitted if it is desirable to do so. A preferred microcavity plasma device includes first and second thin layers that are joined together. A half ellipsoid microcavity or plurality of half ellipsoid microcavities is defined in one or both of the first and second thin layers, and electrodes are arranged with respect to the microcavity to excite a plasma within said microcavities upon application of a predetermined voltage to the electrodes. A method for forming a microcavity plasma device having a plurality of half or full ellipsoid microcavities in one or both of first and second thin layers is also provided by a preferred embodiment. The method includes defining a pattern of protective polymer on the first thin layer. Powder blasting forms half ellipsoid microcavities in the first thin layer. The second thin layer is joined to the first layer. The patterning can be conducted lithographically or can be conduced with a simple screen.
摘要翻译：本发明提供了形成为也密封等离子体介质即气体和/或蒸汽的层的微腔等离子体装置和阵列。不需要单独的包装层，如果要这样做，可以省略额外的包装。优选的微腔等离子体装置包括连接在一起的第一和第二薄层。半椭圆形微腔或多个半椭圆形微腔被限定在第一和第二薄层中的一个或两个中，并且相对于微腔布置电极，以在对电极施加预定电压时在所述微腔内激发等离子体。优选实施例也提供了一种在第一和第二薄层中的一个或两个中形成具有多个半或全椭圆形微腔的微腔等离子体装置的方法。该方法包括在第一薄层上限定保护性聚合物的图案。粉末喷射在第一薄层中形成半椭圆形微腔。第二薄层连接到第一层。图案化可以光刻地进行，或者可以用简单的屏幕进行。

5. 发明授权

US08968668B2 Arrays of metal and metal oxide microplasma devices with defect free oxide 有权
标题翻译：具有缺陷氧化物的金属和金属氧化物微质体装置阵列
公开(公告)号：US08968668B2
公开(公告)日：2015-03-03
申请号：US13527842
申请日：2012-06-20
申请人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
发明人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
IPC分类号： B01J19/08 , H01J37/32 , C25D11/02 , H01J11/18 , C25D11/12 , C25D11/18 , C25D11/26 , H01J17/16
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/00842 , B01J2219/00853 , B01J2219/00891 , C01B13/115 , C25D11/02 , C25D11/022 , C25D11/026 , C25D11/12 , C25D11/18 , C25D11/26 , H01J11/18 , H01J11/22 , H01J11/34 , H01J17/066 , H01J17/16 , H01J37/32055 , H05H2001/2412 , H05H2001/2418
摘要： A microplasma device of the invention includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel upon application of suitable voltage and at least one of the electrodes is encapsulated within the thick metal oxide layer. Large arrays can be formed and are highly robust as lack of microcracks in the oxide avoid dielectric breakdown.
摘要翻译：本发明的微血管装置包括至少部分地限定在基本上由无缺氧氧化物组成的厚金属氧化物层内的微腔或微通道。电极相对于微腔或微通道布置，以在施加适当电压时刺激所述微腔或微通道中的等离子体产生，并且至少一个电极被封装在厚金属氧化物层内。可以形成大阵列，并且由于在氧化物中缺少微裂纹以避免电介质击穿，因此它们具有很强的鲁棒性。

6. 发明授权

US08179032B2 Ellipsoidal microcavity plasma devices and powder blasting formation 有权
标题翻译：椭球微腔等离子体装置和粉末爆破形成
公开(公告)号：US08179032B2
公开(公告)日：2012-05-15
申请号：US12235796
申请日：2008-09-23
申请人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
IPC分类号： H01J1/00 , H01J1/88
CPC分类号： H01J65/046 , H01J9/241 , H01J11/18
摘要： The invention provides microcavity plasma devices and arrays that are formed in layers that also seal the plasma medium, i.e., gas(es) and/or vapors. No separate packaging layers are required and additional packaging can be omitted if it is desirable to do so. A preferred microcavity plasma device includes first and second thin layers that are joined together. A half ellipsoid microcavity or plurality of half ellipsoid microcavities is defined in one or both of the first and second thin layers, and electrodes are arranged with respect to the microcavity to excite a plasma within said microcavities upon application of a predetermined voltage to the electrodes. A method for forming a microcavity plasma device having a plurality of half or full ellipsoid microcavities in one or both of first and second thin layers is also provided by a preferred embodiment. The method includes defining a pattern of protective polymer on the first thin layer. Powder blasting forms half ellipsoid microcavities in the first thin layer. The second thin layer is joined to the first layer. The patterning can be conducted lithographically or can be conduced with a simple screen.
摘要翻译：本发明提供了形成为也密封等离子体介质即气体和/或蒸汽的层的微腔等离子体装置和阵列。不需要单独的包装层，如果要这样做，可以省略额外的包装。优选的微腔等离子体装置包括连接在一起的第一和第二薄层。半椭圆形微腔或多个半椭圆形微腔被限定在第一和第二薄层中的一个或两个中，并且相对于微腔布置电极，以在对电极施加预定电压时在所述微腔内激发等离子体。优选实施例也提供了一种在第一和第二薄层中的一个或两个中形成具有多个半或全椭圆形微腔的微腔等离子体装置的方法。该方法包括在第一薄层上限定保护性聚合物的图案。粉末喷射在第一薄层中形成半椭圆形微腔。第二薄层连接到第一层。图案化可以光刻地进行，或者可以用简单的屏幕进行。

7. 发明授权

US09590089B2 Variable gate width for gate all-around transistors 有权
标题翻译：栅极全能晶体管的可变栅极宽度
公开(公告)号：US09590089B2
公开(公告)日：2017-03-07
申请号：US13997162
申请日：2011-12-30
申请人： Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jack T. Kavalieros , Robert S. Chau , Seung Hoon Sung
发明人： Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jack T. Kavalieros , Robert S. Chau , Seung Hoon Sung
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/06 , H01L29/10 , H01L29/786 , B82Y10/00 , B82Y40/00
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L21/02603 , H01L21/30604 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66613 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696 , H01L2029/7858 , Y10S977/762 , Y10S977/89 , Y10S977/938
摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.
摘要翻译：本文描述了具有一个或多个活性纳米线和一个或多个非活性纳米线的基于纳米线的栅极全周极晶体管器件。还描述了制造这种装置的方法。本发明的一个或多个实施例涉及用于改变包括具有不同数量的纳米线的纳米线堆叠的晶体管结构的栅极宽度的方法。这些方法包括使一定数量的纳米线无效（即使得电流不流过纳米线），通过切断沟道区，掩埋源区和漏区，或两者。总之，具有多个纳米线的纳米线基结构的栅极宽度可以通过使一定数量的纳米线无效而保持其它纳米线作为活性而变化。

8. 发明申请

US20150206796A1 III-N DEVICES IN SI TRENCHES 有权
标题翻译： III-N装置
公开(公告)号：US20150206796A1
公开(公告)日：2015-07-23
申请号：US14162717
申请日：2014-01-23
申请人： Sansaptak Dasgupta , Han Wui Then , Sanaz K. Gardner , Seung Hoon Sung , Marko Radosavljevic , Benjamin Chu-Kung , Sherry R. Taft , Ravi Pillarisetty , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Sanaz K. Gardner , Seung Hoon Sung , Marko Radosavljevic , Benjamin Chu-Kung , Sherry R. Taft , Ravi Pillarisetty , Robert S. Chau
IPC分类号： H01L21/768 , H01L21/762 , H01L21/02
CPC分类号： H01L29/2003 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L21/76229 , H01L21/76232 , H01L21/8258 , H01L29/045 , H01L29/0649 , H01L29/0684
摘要： A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.
摘要翻译：形成包括基板的一部分的沟槽。成核层沉积在沟槽内的衬底部分上。在成核层上沉积III-N材料层。在沟槽上横向生长III-N材料层。器件层沉积在横向生长的III-N材料层上。在横向生长的材料上获得低缺陷密度区域，并用于Si衬底上的III-N材料的电子器件制造。

9. 发明申请

US20150187924A1 Low Sheet Resistance GaN Channel on Si Substrates Using InAlN and AlGaN Bi-Layer Capping Stack 有权
标题翻译：使用InAlN和AlGaN双层封盖叠层的Si衬底上的低片电阻GaN沟道
公开(公告)号：US20150187924A1
公开(公告)日：2015-07-02
申请号：US14141304
申请日：2013-12-26
申请人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Sanaz K. Gardner , Seung Hoon Sung , Benjamin Chu-Kung , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Sanaz K. Gardner , Seung Hoon Sung , Benjamin Chu-Kung , Robert S. Chau
IPC分类号： H01L29/778 , H01L21/306 , H01L29/66
CPC分类号： H01L29/7783 , H01L21/30612 , H01L21/30617 , H01L29/155 , H01L29/2003 , H01L29/4236 , H01L29/66462 , H01L29/7786
摘要： Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.
摘要翻译：晶体管或晶体管层包括2DEG GaN沟道上的InAlN和AlGaN双层封装叠层，例如用于Si衬底上的GaN MOS结构。 GaN沟道可以形成在GaN缓冲层或堆叠中，以补偿GaN和Si之间的高晶格结构晶格尺寸和热膨胀失配系数。双层封装在下AlGaN层上堆叠上InAlN层以在沟道中引起电荷极化，补偿较差的组成均匀性（例如Al），并补偿InAlN材料的底表面的粗糙表面形态。它可能导致250和350欧姆/ sqr之间的薄层电阻。还可以在InAlN材料层的生长期间减少Si晶片上的GaN的弯曲，并且提供用于蚀刻栅极区域中的InAlN层的AlGaN回填层。

10. 发明申请

US20140291693A1 GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES 有权
标题翻译：纳米晶体结构的III-N族晶体管
公开(公告)号：US20140291693A1
公开(公告)日：2014-10-02
申请号：US14303513
申请日：2014-06-12
申请人： Han Wui THEN , Sansaptak Dasgupta , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz Gardner , Seung Hoon Sung , Robert S. Chau
发明人： Han Wui THEN , Sansaptak Dasgupta , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz Gardner , Seung Hoon Sung , Robert S. Chau
IPC分类号： H01L29/20 , H01L29/78
CPC分类号： H01L29/2003 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/201 , H01L29/42356 , H01L29/66462 , H01L29/66795 , H01L29/7787 , H01L29/78 , H01L29/785 , H01L29/7851 , H01L29/802
摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
摘要翻译： III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。

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